Page 1
The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7709S Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series Rev.5.00 2003.9.18...
Page 3
Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series SH7709S Group Hardware Manual REJ09B0081-0500O...
Page 4
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination.
Page 5
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 6
Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Page 7
To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. Purpose: This manual provides the information of the hardware functions and electrical characteristics of the SH7709S. The SH3, SH-3E, SH3-DSP Programming Manual contains detailed information of executable instructions. Please read the Programming Manual together with this manual.
Page 8
User manuals for development tools Name of Document Document No. C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual ADE-702-246 Simulator/Debugger User’s Manual ADE-702-186 Embedded Workshop User’s Manual ADE-702-201 Rev. 5.00, 09/03, page viii of xliv...
Page 9
List of Items Revised or Added for This Version Section Page Description 1.2 Block Diagram ASERAM deleted from figure Figure 1.1 Block BRIDGE Diagram INTC CPG/WDT External bus interface ASERAM deleted from legend 2.5.1 Processor States Description amended In the power-on reset state, the internal states of the CPU and the on-chip supporting module registers are initialized.
Page 10
Section Page Description 5.4.3 Examples of 115, (1) Invalidating a Specific Entry Usage Description amended A specific cache entry can be invalidated by accessing the allocated memory cache and writing a 0 to the entry’s U and V bits. The A bit is cleared to 0, and an address is specified for the entry address and the way.
Page 11
Section Page Description 8.3.3 Precautions Newley added when Using the Sleep Mode 8.5.1 Transition to Note *3 added to bit table Module Standby Note: 3. Before putting the RTC into module standby status, first Function access one or more of the RTC, SCI, and TMU registers.
Page 12
Section Page Description 10.2.13 MCS0 Control Description added Register (MCSCR0) Bit 6—CS2/CS0 Select (CS2/0) Only 0 should be used for the CS2/0 bit in MCSCR0. Either 0 or 1 may be used for MCSCR1 to MCSCR7. 10.3.4 Synchronous Bank Active description added DRAM Interface …...
Page 13
Section Page Description 16.4 SCIF Interrupts Description amended When the TDFE flag in the serial status register (SCSSR) is set to 1, a TXI interrupt request is generated. The DMAC can be activated and data transfer performed when this interrupt is generated.
Page 14
Section Page Description 20.3 Bus Master Figure amended Interface Upper byte read Figure 20.2 A/D Data Register Access Module internal data bus Operation (Reading receives interface H'AA40) data H'AA TEMP [H'40] ADDRn H ADDRn L n = A to D [H'AA] [H'40] Lower byte read...
Page 15
Section Page Description 23.3.6 Synchronous Tnop cycle deleted from figure DRAM Timing Tc3/Td1 Tc4/Td2 Figure 23.31 Synchronous DRAM CKIO Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency A25 to A16 Row address = 2) Read command A12 or A10 Column address A15 to A0 CSD3...
Page 16
Section Page Description A.2 Pin Specifications Function information amended for V –RTC, V –PLL1, V – PLL2, and V Table A.2 Pin Specifications Pin No. Pin No. Function (FP-208C, (BP- FP-208E) 240A) – Power RTC oscillator power supply supply (2.0/1.9/1.8/1.7 V) –...
Page 24
12.3 TMU Operation ......................... 400 12.3.1 General Operation ....................400 12.3.2 Input Capture Function..................403 12.4 Interrupts ........................... 404 12.4.1 Status Flag Setting Timing ................... 404 12.4.2 Status Flag Clearing Timing................. 405 12.4.3 Interrupt Sources and Priorities ................405 12.5 Usage Notes........................406 12.5.1 Writing to Registers....................
Page 25
13.4.3 Precautions when Using RTC Module Standby ........... 426 Section 14 Serial Communication Interface (SCI) ............. 427 14.1 Overview ........................... 427 14.1.1 Features ........................ 427 14.1.2 Block Diagram ..................... 428 14.1.3 Pin Configuration ....................431 14.1.4 Register Configuration ..................432 14.2 Register Descriptions......................
Page 26
15.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode ....507 15.4.2 Retransmission (Receive and Transmit Modes) ........... 509 Section 16 Serial Communication Interface with FIFO (SCIF) ......511 16.1 Overview ........................... 511 16.1.1 Features ........................ 511 16.1.2 Block Diagram ..................... 512 16.1.3 Pin Configuration ....................
Page 27
18.3.1 Port A Control Register (PACR)................570 18.3.2 Port B Control Register (PBCR) ................571 18.3.3 Port C Control Register (PCCR) ................572 18.3.4 Port D Control Register (PDCR) ................573 18.3.5 Port E Control Register (PECR)................574 18.3.6 Port F Control Register (PFCR) ................575 18.3.7 Port G Control Register (PGCR) ................
Page 28
19.11.1 Register Description ..................... 605 19.11.2 Port K Data Register (PKDR) ................606 19.12 Port L..........................607 19.12.1 Register Description ..................... 607 19.12.2 Port L Data Register (PLDR) ................608 19.13 SC Port ..........................609 19.13.1 Register Description ..................... 609 19.13.2 SC Port Data Register (SCPDR) ................
Page 30
Treatment of Unused Pins ....................724 Pin States in Access to Each Address Space ..............725 Appendix B Memory-Mapped Control Registers ............739 Register Address Map ....................... 739 Register Bits ........................745 Appendix C Product Lineup ..................... 757 Appendix D Package Dimensions ...................
Page 32
Figure 8.3 Manual Reset STATUS Output................193 Figure 8.4 Standby to Interrupt STATUS Output..............194 Figure 8.5 Standby to Power-On Reset STATUS Output............195 Figure 8.6 Standby to Manual Reset STATUS Output............196 Figure 8.7 Sleep to Interrupt STATUS Output ..............196 Figure 8.8 Sleep to Power-On Reset STATUS Output............
Page 33
Figure 10.28 Synchronous DRAM Mode Write Timing ............303 Figure 10.29 Burst ROM Wait Access Timing ................. 305 Figure 10.30 Burst ROM Basic Access Timing ................ 306 Figure 10.31 Example of PCMCIA Interface ................308 Figure 10.32 Basic Timing for PCMCIA Memory Card Interface ..........310 Figure 10.33 Wait Timing for PCMCIA Memory Card Interface ..........
Page 34
Figure 11.23 Timing Chart of Source Address Reload Function..........373 Figure 11.24 Block Diagram of CMT ..................376 Figure 11.25 Counter Operation ....................380 Figure 11.26 Count Timing ....................... 381 Figure 11.27 CMF Setting Timing .................... 382 Figure 11.28 Timing of CMF Clearing by the CPU ..............382 Figure 12.1 Block Diagram of TMU ..................
Page 35
Figure 14.17 Data Format in Synchronous Communication ............. 474 Figure 14.18 Sample Flowchart for SCI Initialization............... 476 Figure 14.19 Sample Flowchart for Transmitting Serial Data ........... 477 Figure 14.20 Example of SCI Transmit Operation ..............478 Figure 14.21 Sample Flowchart for Receiving Serial Data ............480 Figure 14.22 Example of SCI Receive Operation..............
Page 36
Figure 19.8 Port H ........................601 Figure 19.9 Port J ........................603 Figure 19.10 Port K ........................605 Figure 19.11 Port L........................607 Figure 19.12 SC Port ......................... 609 Figure 20.1 Block Diagram of A/D Converter ................ 614 Figure 20.2 A/D Data Register Access Operation (Reading H'AA40) ........
Page 37
Figure 23.19 Burst ROM Bus Cycle (No Wait) ................ 678 Figure 23.20 Burst ROM Bus Cycle (Two Waits) ..............679 Figure 23.21 Burst ROM Bus Cycle (External Wait, WAITSEL = 1) ........680 Figure 23.22 Synchronous DRAM Read Bus Cycle (RCD 0, CAS Latency 1, TPC 0) ..
Page 40
Table 10.12 8-Bit External Device/Little-Endian Access and Data Alignment......264 Table 10.13 Relationship between Bus Width, AMX Bits, and Address Multiplex Output ..279 Table 10.14 Example of Correspondence between SH7709S and Synchronous DRAM Address Pins (AMX [3:0] = 0100 (32-Bit Bus Width)).......... 281 Table 10.15 MCSCRx Settings and MCS[x] Assertion Conditions (x: 0–7)......
Page 42
Table 19.1 Port A Register ....................... 587 Table 19.2 Port A Data Register (PADR) Read/Write Operations ........... 588 Table 19.3 Port B Register......................589 Table 19.4 Port B Data Register (PBDR) Read/Write Operations ........... 590 Table 19.5 Port C Register......................591 Table 19.6 Port C Data Register (PCDR) Read/Write Operations ...........
Page 43
Table A.9 Pin States (PCMCIA/Little Endian)................ 735 Table A.10 Pin States (PCMCIA/Big Endian) ................737 Table B.1 Memory-Mapped Control Registers ............... 739 Table B.2 Register Bits ......................745 Table C.1 SH7709S Models....................757 Rev. 5.00, 09/03, page xliii of xliv...
Section 1 Overview and Pin Functions SH7709S Features This LSI is a single-chip RISC microprocessor that integrates a Renesas Technology-original RISC-type SuperH architecture CPU as its core that has an on-chip multiplier, cache memory, and a memory management unit (MMU) as well as peripheral functions required for system configuration such as a timer, a realtime clock, an interrupt controller, and a serial communication interface.
Table 1.1 SH7709S Features Item Features Original Renesas Technology SuperH architecture Object code level with SH-1, SH-2, and SH-3 Series 32-bit internal data bus General-register files Sixteen 32-bit general registers (eight 32-bit shadow registers) Eight 32-bit control registers Four 32-bit system registers...
Page 47
Item Features Cache memory 16-kbyte cache, mixed instruction/data 256 entries, 4-way set associative, 16-byte block length Write-back, write-through, LRU replacement algorithm 1-stage write-back buffer Maximum 2 ways of the cache can be locked Interrupt 23 external interrupt pins (NMI, IRQ5–IRQ0, PINT15 to PINT0) controller (INTC) On-chip peripheral interrupts: set priority levels for each module User break...
Page 48
Output range: 0–AVcc (max. 3.6 V) Product lineup Power Supply Voltage Operating Abbr. Internal Frequency Model Name Package SH7709S 3.3±0.3 V 2.0±0.15 V * 200 MHz HD6417709SHF200B 208-pin plastic HQFP (FP-208E) 1.9±0.15 V 167 MHz HD6417709SF167B 208-pin plastic LQFP (FP-208C)
B C D E F G H L M N P R T U V W SH7709S BP-240A (Top view) B C D E F G H L M N P R T U V W Note: The pin area enclosed in broken lines is an inner view.
1.3.2 Pin Function Table 1.3 SH7709S Pin Function Number of Pins FP-208C FP-208E BP-240A Pin Name Description Clock mode setting Clock mode setting Vcc-RTC * RTC power supply ( * — XTAL2 On-chip RTC crystal oscillator pin EXTAL2 On-chip RTC crystal oscillator...
Page 54
Number of Pins FP-208C FP-208E BP-240A Pin Name Description — Power supply (0 V) — — Power supply (0 V) D19/PTA[3] Data bus / input/output port A Power supply (1.9 V/1.8 V * — Power supply ( * — — D18/PTA[2] Data bus / input/output port A D17/PTA[1]...
Page 55
Number of Pins FP-208C FP-208E BP-240A Pin Name Description VssQ — Input/output power supply (0 V) Address bus VccQ — Input/output power supply (3.3 V) Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus VssQ —...
Page 56
Number of Pins FP-208C FP-208E BP-240A Pin Name Description BS/PTK[4] O / I/O Bus cycle start signal / input/output port K Read strobe WE0/DQMLL D7–D0 select signal / DQM (SDRAM) WE1/DQMLU/WE D15–D8 select signal / DQM (SDRAM) WE2/DQMUL/ICIORD/ O / I/O D23–D16 select signal / DQM PTK[6] (SDRAM) / PCMCIA I/O read /...
Page 57
Number of Pins FP-208C FP-208E BP-240A Pin Name Description RAS3L/PTJ[0] O / I/O Lower 32 M / 64 Mbytes address (SDRAM) RAS / input/output port J Input/output port J * PTJ[1] O / I/O CASL/PTJ[2] O / I/O Lower 32 M / 64 Mbytes address (SDRAM) CAS / input/output port J VssQ —...
Page 58
Number of Pins FP-208C FP-208E BP-240A Pin Name Description AUDATA[3]/PTG[3] I/O / I AUD data / input port G AUDATA[2]/PTG[2] I/O/I AUD data / input port G — Power supply (0 V) — — Power supply (0 V) AUDATA[1]/PTG[1] I/O / I AUD data / input port G Power supply ( * —...
Page 59
Number of Pins FP-208C FP-208E BP-240A Pin Name Description — — Power supply (0 V) Power supply ( * — Power supply ( * — — XTAL Clock oscillator pin EXTAL External clock / crystal oscillator STATUS0/PTJ[6] O / I/O Processor status / input/output port J STATUS1/PTJ[7]...
Page 60
Number of Pins FP-208C FP-208E BP-240A Pin Name Description CTS2/IRQ5/SCPT[7] Transmit clear 2 / external interrupt request / SCI input port MCS[7]/PTC[7]/PINT[7] O / I/O / I Mask ROM chip select / input/output port C / port interrupt MCS[6]/PTC[6]/PINT[6] O / I/O / I Mask ROM chip select / input/output port C / port interrupt MCS[5]/PTC[5]/PINT[5] O / I/O / I Mask ROM chip select /...
Page 61
Number of Pins FP-208C FP-208E BP-240A Pin Name Description AVss — Analog power supply (0 V) AN[0]/PTL[0] A/D converter input / input port L AN[1]/PTL[1] A/D converter input / input port L AN[2]/PTL[2] A/D converter input / input port L AN[3]/PTL[3] A/D converter input / input port L AN[4]/PTL[4]...
Processor Modes: There are two processor modes: user mode and privileged mode. The SH7709S normally operates in user mode, and enters privileged mode when an exception occurs or an interrupt is accepted. There are three kinds of registers—general registers, system registers, and control registers—and the registers that can be accessed differ in the two processor modes.
Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values Initial Value * Type Registers General registers R0 to R15 Undefined Control registers MD bit = 1, RB bit = 1, BL bit = 1, I3–I0 = 1111 (H'F), reserved bits = 0, others undefined GBR, SSR, SPC...
2.1.3 System Registers System registers can be accessed by the LDS and STS instructions. When an exception occurs, the contents of the program counter (PC) are saved in the saved program counter (SPC). The SPC contents are restored to the PC by the RTE instruction used at the end of the exception handling. There are four system registers, as follows.
Saved Status Register (SSR) Stores current SR value at time of exception to indicate processor status in return to instruction stream from exception handler. Saved Program Counter (SPC) Stores current PC value at time of exception to indicate return address at completion of exception handling.
Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits, figure 2.6). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. Longword Figure 2.6 Longword 2.2.2...
2.3.1 Execution Environment Data Length: The SH7709S instruction set is implemented with fixed-length 16-bit wide instructions executed in a pipelined sequence with single-cycle execution for most instructions. All operations are executed in 32-bit longword units. Memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword units, with byte or word units sign-extended into 32-bit longwords.
Page 71
T bit: The T bit in the status register (SR) is used to indicate the result of compare operations, and is read as a TRUE/FALSE condition determining if a conditional branch is taken or not. To improve processing speed, the T bit logic state is modified only by specific operations. An example of how the T bit may be used in a sequence of operations is shown below.
2.3.2 Addressing Modes Addressing modes and effective address calculation methods are shown in table 2.2. Table 2.2 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Effective Address Calculation Method Calculation Formula Register direct Rn Effective address is register Rn. (Operand is —...
Page 73
Addressing Instruction Mode Format Effective Address Calculation Method Calculation Formula Register @(disp:4, Effective address is register Rn contents with Byte: Rn + disp indirect with 4-bit displacement disp added. After disp is Word: Rn + disp displacement zero-extended, it is multiplied by 1 (byte), 2 Longword: Rn + disp (word), or 4 (longword), according to the operand size.
Page 74
Addressing Instruction Mode Format Effective Address Calculation Method Calculation Formula PC-relative @(disp:8, Effective address is register PC contents Word: PC + disp with with 8-bit displacement disp added. After Longword: displacement disp is zero-extended, it is multiplied by 2 PC & H'FFFF FFFC + (word), or 4 (longword), according to the disp operand size.
Page 75
Addressing Instruction Mode Format Effective Address Calculation Method Calculation Formula PC-relative Effective address is sum of register PC and PC + Rn Rn contents. PC + R0 Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, — or XOR instruction is zero-extended. #imm:8 8-bit immediate data imm of MOV, ADD, or —...
2.3.3 Instruction Formats Table 2.3 explains the meaning of instruction formats and source and destination operands. The meaning of the operands depends on the operation code. The following symbols are used. xxxx: Operation code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd:...
Page 77
Source Destination Instruction Instruction Format Operand Operand Example nm format mmmm: register nnnn: register Rm,Rn direct direct xxxx nnnn mmmm xxxx mmmm: register nnnn: register MOV.L indirect indirect Rm,@Rn mmmm: register MACH,MACL MAC.W indirect with post- @Rm+,@Rn+ increment (multiply-and- accumulate operation) nnnn: * register indirect with post-...
Page 78
Source Destination Instruction Instruction Format Operand Operand Example mmmm: register nnnndddd: MOV.L format direct register Rm,@(disp,Rn) xxxx nnnn mmmm dddd indirect with displacement mmmmdddd: nnnn: register MOV.L register indirect direct @(disp,Rm),Rn with displacement d format dddddddd: GBR R0 (register MOV.L indirect with direct) @(disp,GBR),R...
Instruction Set 2.4.1 Instruction Set Classified by Function The SH7709S instruction set includes 68 basic instruction types, as listed in table 2.4. Table 2.4 Classification of Instructions Operation No. of Classification Types Code Function Instructions Data transfer Data transfer MOVA...
Page 80
Operation No. of Classification Types Code Function Instructions Arithmetic Double-precision multiplication (32 operations bits) (cont) MULS Signed multiplication (16 16 bits) MULU Unsigned multiplication (16 16 bits) Negation NEGC Negation with borrow Binary subtraction SUBC Binary subtraction with borrow SUBV Binary subtraction with underflow check Logic Logical AND...
Page 81
Operation No. of Classification Types Code Function Instructions Branch Conditional branch, delayed conditional branch (T Conditional branch, delayed conditional branch (T Unconditional branch BRAF Unconditional branch Branch to subroutine procedure BSRF Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure System CLRMAC...
Table 2.7 lists the SH7709S arithmetic instructions. Table 2.7 Arithmetic Instructions Privileged Instruction Operation Code Mode Cycles T Bit Rn + Rm — — Rm,Rn 0011nnnnmmmm1100 Rn + imm — — #imm,Rn 0111nnnniiiiiiii Rn + Rm + T — Carry...
Page 86
Privileged Instruction Operation Code Mode Cycles T Bit 2(to 5) * — Signed operation of — DMULS.L Rm,Rn 0011nnnnmmmm1101 MACH, MACL 32 64 bits 2(to 5) * — Unsigned operation of — DMULU.L Rm,Rn 0011nnnnmmmm0101 MACH, MACL 32 64 bits Rn –...
Page 87
Privileged Instruction Operation Code Mode Cycles T Bit 0–Rm — — Rm,Rn 0110nnnnmmmm1011 0–Rm–T — Borrow NEGC Rm,Rn 0110nnnnmmmm1010 Borrow Rn–Rm — — Rm,Rn 0011nnnnmmmm1000 Rn–Rm–T — Borrow SUBC Rm,Rn 0011nnnnmmmm1010 Borrow Rn–Rm — Underflow SUBV Rm,Rn 0011nnnnmmmm1011 Underflow Note: * The normal number of execution cycles is shown. The value in parentheses is the number of cycles required in case of contention with the preceding or following instruction.
Table 2.10 lists the SH7709S branch instructions. Table 2.10 Branch Instructions Privileged Instruction Operation Code Mode Cycles T Bit 3/1 * If T 0, disp 2 + PC — — label 10001011dddddddd if T 1, nop 2/1 * Delayed branch, if T —...
2.5.1 Processor States The SH7709S has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The CPU enters the power-on reset state if the RESETP pin is low, or the manual reset state if the RESETM pin is low.
From any state when From any state but hardware standby RESETP = 0 mode when RESETM = 0 RESETP = 0 Power-on reset Manual reset state state Reset state RESETP = 1 RESETM = 1 Exception-handling state Interrupt End of exception Exception transition interrupt...
Overview 3.1.1 Features The SH7709S has an on-chip memory management unit (MMU) that implements address translation. The SH7709S features a resident translation look-aside buffer (TLB) that caches information for user-created address translation tables located in external memory. It enables high- speed translation of virtual addresses into physical addresses.
Page 100
(usually of 1 to 64 kbytes) called a page. This LSI uses the paging method. In the following text, the SH7709S address space in virtual memory is referred to as virtual address space, and address space in physical memory as physical memory space.
Virtual memory Process 1 Process 1 Physical Physical Physical memory memory memory Process 1 Virtual Process 1 Process 1 memory Physical Physical memory memory Process 2 Process 2 Process 3 Process 3 Figure 3.1 MMU Functions Rev. 5.00, 09/03, page 57 of 760...
3.1.3 SH7709S MMU Virtual Address Space: The SH7709S uses 32-bit virtual addresses to access a 4-Gbyte virtual address space that is divided into several areas. Address space mapping is shown in figure 3.2. Privileged Mode In privileged mode, there are five areas, P0–P4. The P0 and P3 areas are mapped onto physical address space in page units, in accordance with address translation table information.
User mode Figure 3.2 Virtual Address Space Mapping Physical Address Space: The SH7709S supports a 32-bit physical address space, but the upper 3 bits are actually ignored and treated as a shadow. See section 10, Bus State Controller (BSC), for details.
Page 104
When the MMU is disabled, the virtual address is used directly as the physical address. As the SH7709S supports a 29-bit address space as the physical address space, the top 3 bits of the physical address are ignored, and constitute a shadow space (see section 10, Bus State Controller (BSC)).
3.1.4 Register Configuration A register that has an undefined initial value must be initialized by software. Table 3.1 shows the configuration of the MMU control registers. Table 3.1 Register Configuration Initial Value * Name Abbreviation Size Address Page table entry register high PTEH Longword Undefined...
5. The MMU control register (MMUCR) residing at address H'FFFFFFE0, which makes the MMU settings described in figure 3.3. Any program that modifies MMUCR should reside in the P1 or P2 area. The MMU registers are shown in figure 3.3. ASID PTEH 31 29 28...
TLB Functions 3.3.1 Configuration of the TLB The TLB caches address translation table information located in the external memory. The address translation table stores the physical page number translated from the virtual page number and the control information for the page, which is the unit of address translation. Figure 3.4 shows the overall TLB configuration.
3.3.2 TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16 to 12 and ASID bits 4 to 0 in PTEH are used as the index number regardless of the page size. The index number can be generated in two different ways depending on the setting of the IX bit in MMUCR.
Virtual address Index Ways 0−3 VPN(31−17) VPN(11−10) ASID(7−0) PPN(28−10) PR(1−0) SZ C D SH Address array Data array Figure 3.7 TLB Indexing (IX = 0) 3.3.3 TLB Address Comparison The results of address comparison determine whether a specific virtual page number is registered in the TLB.
The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry are compared. ASIDs are compared when there is no sharing between processes (SH 0) but not when there is sharing (SH When single virtual memory is supported (MMUCR.SV 1) and privileged mode is engaged (SR.MD 1), all process resources can be accessed.
3.3.4 Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit is 0, an attempt to write to the page results in an initial page write exception.
MMU Functions 3.4.1 MMU Hardware Management There are two kinds of MMU hardware management as follows: 1. The MMU decodes the virtual address accessed by a process and performs address translation by controlling the TLB in accordance with the MMUCR settings. 2.
3.4.3 MMU Instruction (LDTLB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR to the value specified by PTEH and PTEL, using VPN bits 16–12 specified in PTEH as the index number.
MMUCR SV 0 0 RC 0 TF IX AT Way selection Index PTEH register PTEL register 10 8 ASID V 0 PR SZ C D SH 0 Write Write Ways 0 to 3 VPN(31−17) VPN(11−10) ASID(7−0) PPN(28−10) PR(1−0) SZ C D SH Address array Data array...
1-kbyte page is explained below with reference to figure 3.10. To achieve high-speed operation of the SH7709S cache, an index number is created using virtual address bits 11–4. When a 4-kbyte page is used, virtual address bits 11–4 are included in the offset, and since they are not subject to address translation, they are the same as physical address bits 11–4.
5. The contents of the status register (SR) at the time of the exception are written to the save status register (SSR). 6. The mode (MD) bit in SR is set to 1 to place the SH7709S in the privileged mode. 7. The block (BL) bit in SR is set to 1 to mask any further exception requests.
5. The contents of SR at the time of the exception are written to SSR. 6. The MD bit in SR is set to 1 to place the SH7709S in the privileged mode. 7. The BL bit in SR is set to 1 to mask any further exception requests.
6. The contents of SR at the time of the exception are written into SSR. 7. The mode (MD) bit in SR is set to 1 to place the SH7709S in the privileged mode. 8. The block (BL) bit in SR is set to 1 to mask any further exception requests.
5. The contents of SR at the time of the exception are written to SSR. 6. The MD bit in SR is set to 1 to place the SH7709S in the privileged mode. 7. The BL bit in SR is set to 1 to mask any further exception requests.
Start SH = 0 and (MMUCR.SV = 0 or SR.MD = 0)? VPNs match? VPNs and ASIDs match? V = 1? TLB miss TLB invalid exception exception User mode Privileged mode User or privileged? PR check PR check 00/01 01/11 00/10 R/W? R/W?
Figure 3.13 shows the MMU exception signals in the data access mode. MA WB MA WB MA WB MA WB Handler transition EX MA processing MA WB MMU exception handler MA WB : Exception source stage : Stage cancellation for instruction that has begun execution = Instruction fetch = Instruction decode...
In the address field, specify VPN in bits 16-12 as the index address that selects the entry, W in bits 9-8 to select the way, and H'F2 in bits 31-24 to indicate access to the address array. Selection of the index address depends on the MMUCR.IX setting. The following 2 types of operations on the address array are possible.
(1) TLB Address Array Access Read access Address field 11110010 Data field ASID Write access Address field 11110010 Data field ASID VPN: Virtual page number ASID: Address space identifier Valid bit Don't care bit Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3) (2) TLB Data Array Access Read/write access Address field...
3.6.3 Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry’s V bit. When the A bit is 1, the VPN and ASID specified by the write data is compared to the VPN and ASID within the TLB entry selected by the entry address and data is written to the matching way.
Section 4 Exception Handling Overview 4.1.1 Features Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. In response to an exception handling request due to abnormal termination of the executing instruction, control is passed to a user-written exception handler. However, in response to an interrupt request, normal program execution continues until the end of the executing instruction.
2. The block (BL) bit in SR is set to 1, masking any subsequent exceptions. 3. The mode (MD) bit in SR is set to 1 to place the SH7709S in privileged mode. 4. The register bank (RB) bit in SR is set to 1.
4.2.3 Acceptance of Exceptions Processor resets and interrupts are asynchronous events unrelated to the instruction stream. All exception events are prioritized to establish an acceptance order whenever two or more exception events occur simultaneously. All general exception events occur in a relative order in the execution sequence of an instruction (i.e.
Pipeline Sequence: Instruction n TLB miss (data access) Instruction n + 1 TLB miss (instruction access) Instruction n + 2 RIE (reserved instruction exception) Detection Order: TLB miss (instruction n+1) TLB miss (instruction n) and general illegal instruction exception (instruction n + 2) = simultaneous detection Handling Order: Program Order:...
instruction or delay slot is accepted after execution of the delayed branch instruction. The delay slot here refers either to the next instruction after a delayed unconditional branch instruction or to the next instruction when a delayed conditional branch instruction is true. 4.2.4 Exception Codes Table 4.3 lists the exception codes written to the EXPEVT register (for reset or general...
Register Descriptions There are four registers related to exception handling. These are peripheral module registers, and therefore reside in area P4. They can be accessed by specifying the address in privileged mode only. 1. The exception event register (EXPEVT) resides at address H'FFFFFFD4, and contains a 12-bit exception code.
4.4.1 Reset The reset sequence is used to power up or restart the SH7709S from the initialization state. The RESETP and RESETM signals are sampled every clock cycle, and in the case of a power-on reset, all processing being executed (excluding the RTC) is suspended, all unfinished events are canceled, and reset processing is executed immediately.
2. The BL bit in SR is set to 1, masking any subsequent exceptions (except the NMI interrupt when the BLMSK bit is 1). 3. The MD bit in SR is set to 1 to place the SH7709S in privileged mode. 4. The RB bit in SR is set to 1.
UDI Reset Conditions: UDI reset command input (see section 22.4.3, UDI Reset) Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC H'A0000000. Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to 1 and the interrupt mask bits (I3 to I0) are set to B'1111.
Page 140
TLB invalid exception Conditions: Comparison of TLB addresses shows address match but the TLB entry valid bit (V) is 0. Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31–10). The ASID of PTEH indicates the ASID at the time the exception occurred.
Page 141
CPU address error Conditions: a. Instruction fetch from odd address (4n + 1, 4n + 3) b. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) c. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) d.
Page 142
Illegal slot instruction Conditions: a. When undefined code in a delay slot is decoded Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S b. When an instruction that rewrites PC in a delay slot is decoded Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR c.
4.5.3 Interrupts 1. NMI — Conditions: NMI pin edge detection — Operations: PC after the instruction that receives the interrupt is saved to SPC, and SR at the point the interrupt is accepted is saved to SSR. H'01C0 is set to INTEVT and INTEVT2.
5. On-Chip Peripheral Interrupts — Conditions: The interrupt mask bits in SR are lower than the on-chip module (TMU, RTC, SCI, IrDA, SCIF, A/D, DMAC, WDT, REF) interrupt level and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. —...
Page 145
SPC when exception occurs: The PC saved to SPC when an exception occurs is as shown below: Re-executing-type exceptions: PC of the instruction that caused the exception is set in SPC and re-executed after return from exception handling. If the exception occurred in a delay slot, however, PC of the immediately prior delayed branch instruction is set in SPC.
Section 5 Cache Overview 5.1.1 Features The cache specifications are listed in table 5.1. Table 5.1 Cache Specifications Parameter Specification Capacity 16 kbytes Structure Instruction/data mixed, 4-way set associative Locking Way 2 and way 3 are lockable Line size 16 bytes Number of entries 256 entries/way Write system...
31–10) used for comparison during cache searches. In the SH7709S, the top three of 32 physical address bits are used as shadow bits (see section 10, Bus State Controller (BSC)), and therefore in a normal replace operation the top three bits of the tag address are cleared to 0.
The LRU bits are initialized to 000000 by a power-on reset, but are not initialized by a manual reset. Table 5.2 LRU and Way Replacement (When the cache lock function is not used) LRU (5–0) Way to be Replaced 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, 111111...
… … … … … … … … : Reserved bits. Always 0 when reading. Data written here is also always 0. Cache flush bit. Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all cache entries to 0).
LOAD LOCK LOAD LOCK W2LOCK: Way 2 lock bit. W2LOAD: Way 2 load bit. When W2LOCK = 1 & W2LOAD = 1 & SR, CL = 1, the prefetched data will always be loaded into Way2. In all other conditions the prefetched data will be loaded into the way pointed by LRU.
Table 5.5 Way Replacement when Instructions Except for PREF Instruction Ended Up in a Cache Miss DSP bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be replaced Depends on LRU (table 5.2) Depends on LRU (table 5.2) Depends on LRU (table 5.6) Depends on LRU (table 5.7) Depends on LRU (table 5.8) *: Don't care...
Cache Operation 5.3.1 Searching the Cache If the cache is enabled, whenever instructions or data in memory are accessed the cache will be searched to see if the desired instruction or data is in the cache. Figure 5.4 illustrates the method by which the cache is searched.
5.3.2 Read Access Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The transfer unit is 32 bits. The LRU is updated. Read Miss: An external bus cycle starts and the entry is updated. The way replaced is the one least recently used.
PA (31 4) Longword 0 Longword 1 Longword 2 Longword 3 PA (31 4): Physical address written to external memory Longword 0 3: The line of cache data to be written to external memory Figure 5.5 Write-Back Buffer Configuration 5.3.6 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory.
The following three operations on the address array are possible. (1) Address Array Read Reads the tag address, LRU, U bit, and V bit from the entry that corresponds to the entry address and w`ay that were specified in the address field. No associative operation will be performed, regardless of the value of the associative bit (the A bit).
The following two operations on the data array are possible. Note that these operations will not change the information in the address array. (1) Data Array Read Reads the data at the position selected by the L bits (3-2) of the address field from the entry that corresponds to the entry address and way that were specified in the address field.
5.4.3 Examples of Usage (1) Invalidating a Specific Entry A specific cache entry can be invalidated by accessing the allocated memory cache and writing a 0 to the entry’s U and V bits. The A bit is cleared to 0, and an address is specified for the entry address and the way.
Page 160
In the following example, an address (32-bit) to be purged is specified in R0. MOV.L #H'00000FF0, R1 ; R0, R1 ; The entry address is fetched. MOV.L #H'F0000008, R2 ; R1, R2 ; The start is set to H'F0 and the A bit to 1.
External devices can be notified that an interrupt has been received (IRQOUT): When the SH7709S has released the bus, the external bus master can be notified that an external interrupt, an on-chip peripheral module interrupt, or a memory refresh request has occurred, enabling the bus to be requested.
6.1.3 Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 INTC Pins Name Abbreviation Description Nonmaskable interrupt Input of interrupt request signal, not input pin maskable by the interrupt mask bits in Interrupt input pins IRQ5–IRQ0 Input of interrupt request signals, IRL3–IRL0 maskable by the interrupt mask bits in IRLS3-IRLS0...
Interrupt Sources There are five types of interrupt sources: NMI, IRQ, IRL,PINT, and on-chip peripheral modules. Each interrupt has a priority level (0–16), with 0 the lowest and 16 the highest. Priority level 0 masks an interrupt. 6.2.1 NMI Interrupt The NMI interrupt has the highest priority level of 16.
IRL0/IRLS3–IRLS0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0). Figure 6.2 shows an example of IRL interrupt connection. Table 6.3 shows IRL/IRLS pins and interrupt levels. SH7709S Priority Interrupt IRL3 to IRL0...
I I I I R R R R L L L L 3 3 3 3 –I I I I R R R R L L L L 0 0 0 0 /I I I I R R R R L L L L S S S S 3 3 3 3 –I I I I R R R R L L L L S S S S 0 0 0 0 Pins and Interrupt Levels Table 6.3 I I I I R R R R L3 L3/ / / /...
6.2.4 PINT Interrupts PINT interrupts are input by level from pins PINT0–PINT15. The priority level can be set by interrupt priority register D (IPRD) in a range from 0 to 15, in groups of PINT0–PINT7 and PINT8–PINT15. The PINT0/1 interrupt level should be held until the interrupt is accepted and interrupt handling is started.
6.2.6 Interrupt Exception Handling and Priority Tables 6.4 and 6.5 list the codes for the interrupt event registers (INTEVT and INTEVT2), and the order of interrupt priority. Each interrupt source is assigned a unique code. The start address of the interrupt service routine is common to each interrupt source.
INTC Registers 6.3.1 Interrupt Priority Registers A to E (IPRA–IPRE) Interrupt priority registers A to E (IPRA to IPRE) are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for on-chip peripheral module, IRQ, and PINT interrupts. These registers are initialized to H'0000 by a power-on reset or manual reset, but are not initialized in standby mode.
6.3.2 Interrupt Control Register 0 (ICR0) ICR0 is a register that sets the input signal detection mode of external interrupt input pin NMI, and indicates the input signal level at the NMI pin. This register is initialized to H'0000 or H'8000 by a power-on reset or manual reset, but is not initialized in standby mode.
6.3.3 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ0 to IRQ5 individually: rising edge, falling edge, or low level. This register is initialized to H'4000 by a power-on reset or manual reset, but is not initialized in standby mode.
Page 178
Bit 12—I I I I R R R R L L L L S S S S Enable (IRLSEN): Enables pins IRLS3–IRLS0. This bit is valid only when the IRQLVL bit is 1. Bit 12: IRLSEN Description Pins IRLS3–IRLS0 disabled (Initial value) Pins IRLS3–IRLS0 enabled Bits 11 and 10—IRQ5 Sense Select (IRQ51S, IRQ50S): Select whether the interrupt signal to...
Page 179
Bits 5 and 4—IRQ2 Sense Select (IRQ21S, IRQ20S): Select whether the interrupt signal to the IRQ2 pin is detected at the rising edge, at the falling edge, or at the low level. Bit 5: IRQ21S Bit 4: IRQ20S Description An interrupt request is detected at IRQ2 input falling edge (Initial value) An interrupt request is detected at IRQ2 input rising edge An interrupt request is detected at IRQ2 input low level...
6.3.4 Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit readable/writable register that sets the detection mode for external interrupt input pins PINT0 to PINT15. This register is initialized to H'0000 by a power-on reset or manual reset, but is not initialized in standby mode. Bit: PINT15S PINT14S PINT13S PINT14S PINT11S PINT10S PINT9S PINT8S Initial value:...
6.3.5 PINT Interrupt Enable Register (PINTER) PINTER is a 16-bit readable/writable register that enables interrupt requests input to external interrupt input pins PINT0 to PINT15. This register is initialized to H'0000 by a power-on reset or manual reset, but is not initialized in standby mode. Bit: PINT15E PINT14E PINT13E PINT12E PINT11E PINT10E PINT9E PINT8E Initial value:...
6.3.6 Interrupt Request Register 0 (IRR0) IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to IRQ5 and PINT0 to PINT15. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode.
Page 183
Bit 4—IRQ4 Interrupt Request (IRQ4R): Indicates whether there is interrupt request input to the IRQ4 pin. When edge detection mode is set for IRQ4, an interrupt request is cleared by clearing the IRQ4R bit. Bit 4: IRQ4R Description No interrupt request input to IRQ4 pin (Initial value) Interrupt request input to IRQ4 pin Bit 3—IRQ3 Interrupt Request (IRQ3R): Indicates whether there is interrupt request input to...
6.3.7 Interrupt Request Register 1 (IRR1) IRR1 is an 8-bit read-only register that indicates whether DMAC or IrDA interrupt requests have been generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit: TXI1R BRI1R...
Bit 3—DEI3 Interrupt Request (DEI3R): Indicates whether a DEI3 (DMAC) interrupt request has been generated. Bit 3: DEI3R Description DEI3 interrupt request not generated (Initial value) DEI3 interrupt request generated Bit 2—DEI2 Interrupt Request (DEI2R): Indicates whether a DEI2 (DMAC) interrupt request has been generated.
Page 186
Bits 7 to 5—Reserved: These bits are always read as 0. The write value should always be 0. Bit 4—ADI Interrupt Request (ADIR): Indicates whether an ADI (ADC) interrupt request has been generated. Description it 4: ADIR ADI interrupt request not generated (Initial value) ADI interrupt request generated Bit 3—TXI2 Interrupt Request (TXI2R): Indicates whether a TXI2 (SCIF) interrupt request has...
Notes: 1. The interrupt mask bits (I3–I0) in the status register (SR) are not changed by acceptance of an interrupt in the SH7709S. 2. IRQOUT outputs a low level until the interrupt request is cleared. However, if the interrupt source is masked by an interrupt mask bit, the IRQOUT pin returns to the high level.
6.4.2 Multiple Interrupts When handling multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT and INTEVT2. The code in INTEVT and INTEVT2 can be used as a branch-offset for branching to the specific handler.
Table 6.8 Interrupt Response Time Number of States Peripheral Item PINT Modules Notes Time for priority Icyc Icyc Icyc Icyc decision and SR + 0.5 Bcyc Bcyc + 3.5 Pcyc + 1.5 Pcyc * mask bit comparison + 0.5 Pcyc + 4.5 Pcyc * Icyc...
Page 191
Number of States Peripheral Item PINT Modules Notes Response Total (5.5 + X) (5.5 + X) (5.5 + X) (5.5 + X) time Icyc Icyc Icyc Icyc + 0.5 Bcyc Bcyc + 3.5 + 1.5 Pcyc * Pcyc * + 0.5 Pcyc + 4.5 Pcyc *...
Interrupt Start of interrupt acceptance handling 0.5 × Icyc + 0.5 × Bcyc + 2 × Pcyc 5 × Icyc Instruction (instruction replaced by interrupt exception handling) Overrun fetch First instruction of interrupt handler Instruction fetch: Instruction is fetched from memory in which program is stored. Instruction decode: Fetched instruction is decoded.
Section 7 User Break Controller Overview The user break controller (UBC) provides functions that simplify program debugging. This function makes it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write, data size, data content, address value, and stop timing during instruction fetches.
Register Descriptions 7.2.1 Break Address Register A (BARA) BARA is a 32-bit read/write register. BARA specifies the address used as a break condition in channel A. A power-on reset initializes BARA to H'00000000. Bit: BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 Initial value:...
7.2.3 Break Bus Cycle Register A (BBRA) Break bus cycle register A (BBRA) is a 16-bit read/write register, which specifies (1) CPU cycle or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel A.
Page 199
Bits 3 and 2—Read/Write Select A (RWA1, RWA0): Selects the read cycle or write cycle as the bus cycle of the channel A break condition. Bit 3: RWA1 Bit 2: RWA0 Description Condition comparison is not performed (Initial value) The break condition is the read cycle The break condition is the write cycle The break condition is the read cycle or write cycle Bits 1 and 0—Operand Size Select A (SZA1, SZA0): Selects the operand size of the bus cycle...
7.2.4 Break Address Register B (BARB) BARB is a 32-bit read/write register. BARB specifies the address used as a break condition in channel B. A power-on reset initializes BARB to H'00000000. Bit: BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 Initial value: R/W: Bit:...
7.2.7 Break Data Mask Register B (BDMRB) BDMRB is a 32-bit read/write register. BDMRB specifies bits masked in the break data specified by BDRB. A power-on reset initializes BDMRB to H'00000000. Bit: BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 Initial value: R/W: Bit:...
7.2.8 Break Bus Cycle Register B (BBRB) Break bus cycle register B (BBRB) is a 16-bit read/write register, which specifies, (1) CPU cycle or DMAC cycle, (2) instruction fetch or data access, (3) read/write, and (4) operand size in the break conditions of channel B.
Page 205
Bits 3 and 2—Read/Write Select B (RWB1, RWB0): Select the read cycle or write cycle as the bus cycle of the channel B break condition. Bit 3: RWB1 Bit 2: RWB0 Description Condition comparison is not performed (Initial value) The break condition is the read cycle The break condition is the write cycle The break condition is the read cycle or write cycle Bits 1 and 0—Operand Size Select B (SZB1, SZB0): Select the operand size of the bus cycle for...
7.2.9 Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channels condition or under the sequential condition. 2. A break is set before or after instruction execution. 3. A break is set by the number of execution times. 4.
Page 207
Bit 21—Break ASID Mask A (BASMA): Specifies whether the bits of the channel A break ASID7-ASID0 (BASA7 to BASA0) set in BASRA are masked or not. Bit 21: BASMA Description All BASRA bits are included in break condition, ASID is checked (Initial value) No BASRA bits are included in break condition, ASID is not checked Bit 20—Break ASID Mask B (BASMB): Specifies whether the bits of channel B break ASID7-...
Page 208
Bit 13—DMAC Condition Match Flag A (SCMFDA): When the on-chip DMAC bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. Bit 13: SCMFDA Description...
Page 209
Bit 6—PC Break Select B (PCBB): Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. Bit 6: PCBB Description PC break of channel B is set before instruction execution (Initial value) PC break of channel B is set after instruction execution Bits 5 and 4—Reserved: These bits are always read as 0.
7.2.10 Execution Times Break Register (BETR) When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 2 – 1 times. A power-on reset initializes BETR to H'0000. When a break condition is satisfied, it decreases the BETR. A break is issued when the break condition is satisfied after the BETR becomes H'0001.
7.2.11 Branch Source Register (BRSR) BRSR is a 32-bit read register. BRSR stores the last fetched address before branch and the pointer (3 bits) which indicates the number of cycles from fetch to execution for the last executed instruction. BRSR has the flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRSR is read and also initialized by power-on resets or manual resets.
Bits 30 to 28—Instruction Decode Pointer (PID2 to PID0): PID is a 3-bit binary pointer (0–7). These bits indicate the instruction buffer number which stores the last executed instruction before branch. Bits 30 to 28: Description Even PID indicates the instruction buffer number. PiD+2 indicates the instruction buffer number Bits 27 to 0—Branch Source Address (BSA27 to BSA0): These bits store the last fetched address before branch.
Bit 31—BRDR Valid Flag (DVF): Indicates whether a branch destination address is stored. When a branch destination address is fetched, this flag is set to 1. This flag is set to 0 in reading BRDR. Bit 31: DVF Description The value of BRDR register is invalid The value of BRDR register is valid Bits 30 to 28—Reserved: These bits are always read as 0.
Operation Description 7.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses and the corresponding ASIDs are loaded in the break address registers (BARA and BARB) and break ASID registers (BASRA and BASRB). The masked addresses are set in the break address mask registers (BAMRA and BAMRB).
3. When the condition is specified to be occurred after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions. When this kind of break is set for a delay branch instruction, the break is generated at the instruction that then first accepts the break.
7.3.4 Sequential Break 1. By specifying SEQ in BRCR is set to 1, the sequential break is issued when channel B break condition matches after channel A break condition matches. A user break is ignored even if channel B break condition matches before channel A break condition matches. When channels A and B condition match at the same time, the sequential break is not issued.
7.3.6 PC Trace 1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, repeat, and interrupt) is generated, the address from which the branch source address can be calculated and the branch destination address are stored in BRSR and BRDR, respectively. The branch address and the pointer, which corresponds to the branch, are included in BRSR.
reaches the bottom of the queues. After switching the PCTE bit (in BRCR) off and on, the values in the queues are invalid. The read pointer stay at the position before PCTE is switched, but the trace pointer restart at the bottom of the queues. 7.3.7 Usage Examples Break Condition Specified to a CPU Instruction Fetch Cycle...
7.3.8 Notes 1. Only CPU can read/write UBC registers. 2. UBC cannot monitor CPU and DMAC access in the same channel. 3. Notes in specification of sequential break are described below: a. A condition match occurs when B-channel match occurs in a bus cycle after an A-channel match occurs in another bus cycle in sequential break setting.
In the power-down modes, all CPU and some on-chip peripheral module functions are halted. This lowers power consumption. 8.1.1 Power-Down Modes The SH7709S has the following power-down modes and function: 1. Sleep mode 2. Standby mode 3. Module standby function (TMU, RTC, SCI, UBC, DMAC, DAC, ADC, SCIF, and IrDA on- chip peripheral modules) 4.
Table 8.1 Power-Down Modes State On-Chip Transition Reg- On-Chip Peripheral External Canceling Mode Conditions CPG CPU ister Memory Modules Pins Memory Procedure Sleep Execute SLEEP Runs Halts Held Held Held Refresh 1. Interrupt mode instruction with 2. Reset STBY bit cleared to 0 in STBCR Halt * Standby...
8.1.2 Pin Configuration Table 8.2 lists the pins used for the power-down modes. Table 8.2 Pin Configuration Pin Name Abbreviation Description Processing state 1 STATUS1 Operating state of the processor. Processing state 0 STATUS0 HH: Reset, HL: Sleep mode, LH: Standby mode, LL: Normal operation WAKEUP Wakeup from...
Page 228
Bit 7—Standby (STBY): Specifies transition to standby mode. Bit 7: STBY Description Executing SLEEP instruction puts chip into sleep mode (Initial value) Executing SLEEP instruction puts chip into standby mode Bits 6, 5, and 3—Reserved: These bits are always read as 0. The write value should always be 0. Bit 4—Standby Crystal (STBXTL): Specifies halting or operating of the clock pulse generator in standby mode.
Bit 0—Module Standby 0 (MSTP0): Specifies halting of the clock supply to the serial communication interface SCI (an on-chip peripheral module). When the MSTP0 bit is set to 1, the supply of the clock to the SCI is halted. Bit 0: MSTP0 Description SCI operates (Initial value)
Page 230
Bit 4—Module Stop 7 (MSTP7): Specifies halting of the clock supply to the DMAC (an on-chip peripheral module). When the MSTP7 bit is set to 1, the supply of the clock to the DMAC is halted. Bit 4: MSTP7 Description DMAC runs (Initial value) Clock supply to DMAC halted...
Sleep Mode 8.3.1 Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to run in sleep mode and the clock continues to be output to the CKIO and CKIO2 pins.
Standby Mode 8.4.1 Transition to Standby Mode To enter standby mode, set the STBY bit to 1 in STBCR, then execute the SLEEP instruction. The chip switches from the program execution state to standby mode. In standby mode, power consumption is greatly reduced by halting not only the CPU, but the clock and on-chip peripheral modules as well.
8.4.2 Canceling Standby Mode Standby mode is canceled by an interrupt (NMI, IRQ, IRL, PINT, or on-chip peripheral module) or a reset. Canceling with an Interrupt: The on-chip WDT can be used for hot starts. When the chip detects an NMI, IRL, IRQ, PINT * , or on-chip peripheral module (except interval timer) * interrupt, the clock will be supplied to the entire chip and standby mode canceled after the time set in the...
Canceling with a Reset: Standby mode is canceled by a reset (power-on or manual). Keep the RESET pin low until the clock oscillation settles. The internal clock will continue to be output to the CKIO and CKIO2 pins. 8.4.3 Clock Pause Function In standby mode, the clock input from the EXTAL pin or CKIO pin can be halted and the frequency can be changed.
Module Standby Function 8.5.1 Transition to Module Standby Function Setting the standby control register MSTP8–MSTP0 bits to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the power consumption in normal mode and sleep mode. The module standby function holds the state prior to halting the external pins of the on-chip peripheral modules.
Timing of STATUS Pin Changes The timing of STATUS1 and STATUS0 pin changes is shown in figures 8.1 to 8.8. 8.6.1 Timing for Resets Power-On Reset CKIO, CKIO2* PLL settling time RESETP Normal* Reset* Normal* STATUS RESETOUT 0 to 5 Bcyc* 0 to 30 Bcyc* Notes: 1.
Manual Reset CKIO, CKIO2* RESETM Normal* Reset* Normal* STATUS RESETOUT 0 Bcyc or more* 0 to 30 Bcyc* Notes: 1. In a manual reset, STATUS becomes HH (reset) and the internal reset begins after waiting for the executing bus cycle to end. Reset: HH (STATUS1 high, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low)
Standby to Power-On Reset Oscillation stops Reset CKIO, CKIO2* RESETP* Normal* Standby* Reset* Normal* STATUS 0 to 10 Bcyc* 0 to 30 Bcyc* Notes: 1. When standby mode is cleared with a power-on reset, the WDT does not count. Keep RESETP low during the PLL’s oscillation settling time. Undefined Reset: HH (STATUS1 high, STATUS0 high)
Standby to Manual Reset Oscillation stops Reset CKIO, CKIO2* RESETM* STATUS Normal* Standby* Reset* Normal* 0 to 20 Bcyc* Notes: 1. When standby mode is cleared with a manual reset, the WDT does not count. Keep RESETM low during the PLL’s oscillation settling time. Reset: HH (STATUS1 high, STATUS0 high) Standby: LH (STATUS1 low, STATUS0 high)
Sleep to Power-On Reset Reset CKIO, CKIO2* RESETP* STATUS Normal* Sleep* Reset* Normal* 0 to 10 Bcyc* 0 to 30 Bcyc* Notes: 1. When the PLL1’s multiplication ratio is changed by a power-on reset, keep RESETP low during the PLL’s oscillation settling time. Undefined Reset: HH (STATUS1 high, STATUS0 high)
Hardware Standby Mode 8.7.1 Transition to Hardware Standby Mode Driving the CA pin low causes a transition to hardware standby mode. In hardware standby mode, all modules except those operating on an RTC clock are halted, as in the standby mode entered on execution of a SLEEP instruction ((software) standby mode).
8.7.3 Hardware Standby Mode Timing Figures 8.10 and 8.11 show examples of pin timing in hardware standby mode. The CA pin is sampled using EXTAL2 (32.768 kHz), and a hardware standby request is only recognized when the pin is low for two consecutive clock cycles. The CA pin must be held low while the chip is in hardware standby mode.
Section 9 On-Chip Oscillation Circuits Overview The on-chip oscillation circuits consist of a clock pulse generator (CPG) block and a watchdog timer (WDT) block. The WDT is a single-channel timer that counts the clock settling time and is used when clearing standby mode and temporary standbys, such as frequency changes. It can also be used as an ordinary watchdog timer or interval timer.
Overview of CPG 9.2.1 CPG Block Diagram A block diagram of the on-chip clock pulse generator is shown in figure 9.1. Clock pulse generator Divider 1 CAP1 Internal PLL circuit 1 clock (I ) ( 1, 2, 3, 4, Cycle = Icyc CKIO Cycle = Bcyc CAP2...
Page 249
The clock pulse generator blocks function as follows: 1. PLL Circuit 1: PLL circuit 1 doubles, triples, quadruples, sextuples, or leaves unchanged the input clock frequency from the CKIO pin. The multiplication rate is set by the frequency control register. When this is done, the phase of the leading edge of the internal clock is controlled so that it will agree with the phase of the leading edge of the CKIO pin.
9.2.2 CPG Pin Configuration Table 9.1 lists the CPG pins and their functions. Table 9.1 CPG Pins and Functions Pin Name Symbol Description Mode control Set the clock operating mode pins Crystal I/O pins XTAL Connects a crystal oscillator (clock input pins) EXTAL Connects a crystal oscillator.
Clock Operating Modes Table 9.3 shows the relationship between the mode control pin (MD2–MD0) combinations and the clock operating modes. Table 9.4 shows the usable frequency ranges in the clock operating modes. Table 9.3 Clock Operating Modes Pin Values Clock I/O PLL2 PLL1 Divider 1...
Mode 7: In this mode, the CKIO pin is an input, an external clock is input to this pin, and undergoes waveform shaping, and also frequency multiplication according to the setting, by PLL circuit 1 before being supplied to the chip. In modes 0 to 2, the system clock is generated from the output of the chip’s CKIO pin.
Page 253
Clock Rate * Clock Input Frequency CKIO Frequency Mode FRQCR PLL1 PLL2 (I:B:P) Range Range 1, 2 H'0100 ON ( 1) ON ( 4) 4:4:4 6.25 MHz to 8.34 MHz 25 MHz to 33.34 MHz H'0101 ON ( 1) ON ( 4) 4:4:2 6.25 MHz to 16.67 MHz 25 MHz to 66.67 MHz H'0102 ON ( 1) ON ( 4) 4:4:1...
Page 254
Cautions: 1. The frequency of the internal clock (I ) becomes: • The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 1. • Do not set the internal clock frequency lower than the CKIO pin frequency. 2.
Register Descriptions 9.4.1 Frequency Control Register (FRQCR) The frequency control register (FRQCR) is a 16-bit readable/writable register used to specify the frequency multiplication ratio of PLL circuit 1 and the frequency division ratio of the internal clock and the peripheral clock. Only word access can be used on the FRQCR register.
Page 256
Bits 14, 3, and 2—Internal Clock Frequency Division Ratio (IFC): These bits specify the frequency division ratio of the internal clock with respect to the output frequency of PLL circuit 1. Bit 14: IFC2 Bit 3: IFC1 Bit 2: IFC0 Description (Initial value) Except above value...
Changing the Frequency The frequency of the internal clock and peripheral clock can be changed either by changing the multiplication ratio of PLL circuit 1 or by changing the division ratios of dividers 1 and 2. All of these are controlled by software through the frequency control register. The methods are described below.
WDT Registers 9.7.1 Watchdog Timer Counter (WTCNT) The watchdog timer counter (WTCNT) is an 8-bit readable/writable counter that increments on the selected clock. WTCNT differs from other registers in that it is more difficult to write to. See section 9.7.3, Notes on Register Access, for details. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode.
Page 260
Bit 6—Timer Mode Select (WT/I I I I T T T T ): Selects whether to use the WDT as a watchdog timer or an interval timer. Bit 6: WT/I I I I T T T T Description Used as interval timer (Initial value) Used as watchdog timer Note: If WT/IT is modified when the WDT is running, the up-count may not be performed correctly.
Overflow Period Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Division Ratio (when P = 15 MHz) (Initial value) 17 s 68 s 1/16 273 s 1/32 546 s 1/64 1.09 ms 1/256 4.36 ms 1/1024 17.48 ms 1/4096 69.91 ms Note: If bits CKS2–CKS0 are modified when the WDT is running, the up-count may not be...
WDT. When the STBY bit remains at 1, the SH7709S again enters standby mode when the WDT has counted up to H'80. This standby mode can be canceled by a power-on reset.
When the following three conditions are all met, FRQCR should not be changed while a DMAC transfer is in progress. Bits IFC2 to IFC0 are changed. STC2 to STC0 are not changed. The clock ratio of I (on-chip clock) to B (bus clock) after the change is other than 1:1. 9.8.3 Using Watchdog Timer Mode 1.
Decoupling Capacitors: Insert a laminated ceramic capacitor of 0.1 to 1 F as a passive capacitor for each V pair. Mount the passive capacitors close to the SH7709S power supply pins, and use components with a frequency characteristic suitable for the chip’s operating frequency, as well as a suitable capacitance value.
Section 10 Bus State Controller (BSC) 10.1 Overview The bus state controller (BSC) divides physical address space and output control signals for various types of memory and bus interface specifications. BSC functions enable the chip to link directly with synchronous DRAM, SRAM, ROM, and other memory storage devices without an external circuit.
Page 268
Short refresh cycle control The overflow interrupt function of the refresh counter enables the refresh function immediately after a self-refresh operation using low power-consumption DRAM The refresh counter can be used as an interval timer Outputs an interrupt request signal using the compare-match function Outputs an interrupt request signal when the refresh counter overflows Rev.
10.1.2 Block Diagram Figure 10.1 shows a block diagram of the bus state controller. interface WCR1 Wait WAIT controller WCR2 CS0, CS6 to CS2, Area CE2A, CE2B BCR1 controller MCS0 to MCS7 BCR2 RD/WR WE3 to WE0 RASxx CASx Memory controller ICIORD, ICIOWR MCSCRn...
10.1.3 Pin Configuration Table 10.1 shows the BSC pin configuration. Table 10.1 BSC Pins Pin Name Signal Description Address bus A25–A0 Address output Data bus D15–D0 Data I/O D31–D16 Data I/O when using 32-bit bus width Bus cycle start Shows start of bus cycle. During burst transfers, asserted every data cycle.
Page 271
Pin Name Signal Description WE3/DQMUU/ Data enable 3 When memory other than synchronous DRAM and ICIOWR PCMCIA is used, D31–D24 write strobe signal. When synchronous DRAM is used, selects D31– D24. When PCMCIA is used, strobe signal indicating I/O write. Read Strobe signal indicating read cycle WAIT...
10.1.4 Register Configuration The BSC has 21 registers (table 10.2). Synchronous DRAM also has a built-in synchronous DRAM mode register. These registers control direct connection interfaces to memory, wait states, and refreshes devices. Table 10.2 BSC Registers Initial Value * Address Name Abbr.
3, Memory Management Unit (MMU), which describes area allocation for physical space. As shown in table 10.3, the SH7709S can be connected directly to six memory/PCMCIA interface areas, and it outputs chip select signals (CS0, CS2–CS6, CE2A, CE2B) for each of them. CS0 is asserted during area 0 access;...
Figure 10.3 Physical Space Allocation Memory Bus Width: The memory bus width in the SH7709S can be set for each area. In area 0, external pins can be used to select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset.
10.1.6 PCMCIA Support The SH7709S supports PCMCIA standard interface specifications in physical space areas 5 and 6. The interfaces supported are basically the “IC memory card interface” and “I/O card interface” stipulated in JEIDA Specifications Ver. 4.2 (PCMCIA2.1).
Table 10.6 PCMCIA Support Interface IC Memory Card Interface I/O Card Interface Pin Signal I/O Function Signal I/O Function SH7709S Pin — Ground — Ground — I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data...
Page 278
IC Memory Card Interface I/O Card Interface Pin Signal I/O Function Signal I/O Function SH7709S Pin I/O Data I/O Data I/O Data I/O Data IOIS16 IOIS16 Write protect 16-bit I/O port Ground Ground — Ground Ground — Card detection Card detection —...
IC Memory Card Interface I/O Card Interface Pin Signal I/O Function Signal I/O Function SH7709S Pin Attribute memory Attribute memory — space select space select SPKR BVD2 Battery voltage Digital voice signal — detection STSCHG BVD1 Battery voltage Card state —...
Page 280
The endian for all physical spaces is decided by this bit, which is read-only. Bit 11: ENDIAN Description (On reset) Endian setting external pin (MD5) is low. Indicates the SH7709S is set as big-endian (On reset) Endian setting external pin (MD5) is high. Indicates the SH7709S is set as little-endian Rev.
Page 281
Bits 10 and 9—Area 0 Burst ROM Control (A0BST1, A0BST0): Specify whether to use burst ROM in physical space area 0. When burst ROM is used, these bits set the number of burst transfers. Bit 10: A0BST1 Bit 9: A0BST0 Description Access area 0 accessed as ordinary memory (Initial value)
Page 282
Bit 6: A6BST1 Bit 5: A6BST0 Description Access area 6 accessed as ordinary memory (initial value) Burst access of area 6 (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. Burst access of area 6 (8 consecutive accesses). Can be used when bus width is 8 or 16.
Bit 0—Area 6 Bus Type (A6PCM): Designates whether to access physical space area 6 as PCMCIA space. Bit 0: A6PCM Description Physical space area 6 accessed as ordinary memory (Initial value) Physical space area 6 accessed as PCMCIA space 10.2.2 Bus Control Register 2 (BCR2) Bus control register 2 (BCR2) is a 16-bit readable/writable register that selects the bus size of each area and whether an 8-bit port is used or not.
Bit 2n + 1: AnSZ1 Bit 2n: AnSZ0 Port A / B Description Not used Reserved (Setting prohibited) Byte (8-bit) size Word (16-bit) size Longword (32-bit) size Used Reserved (Setting prohibited) Byte (8-bit) size Word (16-bit) size Reserved (Setting prohibited) 10.2.3 Wait State Control Register 1 (WCR1) Wait state control register 1 (WCR1) is a 16-bit readable/writable register that specifies the...
Bit 15—WAIT Sampling Timing Select (WAITSEL): Specifies the WAIT signal sampling timing. Bit 15: WAITSEL Description Setting to 1 when using the WAIT signal * (Initial value) Sampled WAIT signal at fall of CKIO Note: * Operation is not guaranteed if WAIT is asserted while WEITSEL = 0. Bits 14, 3, and 2 —Reserved: These bits are always read as 0.
Page 286
Bits 15 to 13—Area 6 Wait Control (A6W2, A6W1, A6W0): Specify the number of wait states inserted in physical space area 6. Also specify the number of states for burst transfer. Description Burst Cycle First Cycle (Excluding First Cycle) Bit 15: Bit 14: Bit 13: Inserted...
Page 287
Bits 9 to 7—Area 4 Wait Control (A4W2, A4W1, A4W0): Specify the number of wait states inserted in physical space area 4. Description Inserted Wait State W W W W A A A A I I I I T T T T Pin Bit 9: A4W2 Bit 8: A4W1 Bit 7: A4W0...
Page 288
Bits 4 and 3—Area 2 Wait Control (A2W1, A2W0): Specify the number of wait states inserted in physical space area 2. For Ordinary Memory Description W W W W A A A A I I I I T T T T Pin Bit 4: A2W0 Bit 3: A2W0 Inserted Wait States...
10.2.5 Individual Memory Control Register (MCR) The individual memory control register (MCR) is a 16-bit readable/writable register that specifies RAS and CAS timing for synchronous DRAM (areas 2 and 3), specifies address multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without external circuits. MCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 290
Bits 13 and 12—RAS–CAS Delay (RCD1, RCD0): When synchronous DRAM interface is selected as connected memory, these bits set the bank active read/write command delay time. Bit 13: RCD1 Bit 12: RCD0 Description 1 cycle (Initial value) 2 cycles 3 cycles 4 cycles Bits 11 and 10—Write-Precharge Delay (TRWL1, TRWL0): Set the synchronous DRAM write-precharge delay time.
Page 291
Bits 6 to 3—Address Multiplex (AMX3, AMX2, AMX1, AMX0): Specify address multiplexing for synchronous DRAM. For Synchronous DRAM Interface: Bit6: Bit5: Bit 4: Bit 3: AMX3 AMX2 AMX1 AMX0 Description The row address begins with A10 (The A10 value is output at A1 when the row address is output.
Bit 1—Refresh Mode (RMODE): Selects whether to perform an ordinary refresh or a self- refresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 0, an auto-refresh is performed on synchronous DRAM at the period set by refresh-related registers RTCNT, RTCOR, and RTCSR.
Page 293
Bit 15—Area 6 Wait Control (A6W3): Specifies the number of inserted wait states for area 6 combined with bits A6W2–A6W0 in WCR2. Also specifies the number of transfer states in burst transfer. Clear this bit to 0 when area 6 is not set to PCMCIA. First Cycle Burst Cycle Number of...
Page 294
Bits 11, 7, and 6—Area 5 Address O O O O E E E E /W W W W E E E E Assert Delay (A5TED2, A5TED1, A5TED0): Specify the delay time from address output to OE/WE assertion for the PCMCIA interface connected to area 5.
Page 295
Bits 9, 3, and 2—Area 5 O O O O E E E E /W W W W E E E E Negate Address Delay (A5TEH2, A5TEH1, A5TEH0): Specify the address hold delay time from OE/WE negation for the PCMCIA interface connected to area 5.
10.2.7 Synchronous DRAM Mode Register (SDMR) The synchronous DRAM mode register (SDMR) is an 8-bit write-only register that is written to via the synchronous DRAM address bus. It sets synchronous DRAM mode for areas 2 and 3. SDMR must be set before accessing the synchronous DRAM. Writes to the synchronous DRAM mode register use the address bus rather than the data bus.
10.2.8 Refresh Timer Control/Status Register (RTCSR) The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that specifies the refresh cycle, whether to generate an interrupt, and the cycle of that interrupt. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 298
Bits 5 to 3—Clock Select Bits (CKS2 to CKS0): Select the clock input to RTCNT. The source clock is the external bus clock (CKIO). The RTCNT count clock is CKIO divided by the specified ratio. RTCOR must be set before setting CKS2-CKS0. Description Bit 5: CKS2 Bit 4: CKS1...
Bit 0—Refresh Count Overflow Limit Select (LMTS): Indicates the count limit value to be compared to the number of refreshes indicated in the refresh count register (RFCR). When the value in RFCR overflows the value specified by LMTS, the OVF flag is set. Bit 0: LMTS Description Count limit value is 1024...
10.2.10 Refresh Time Constant Register (RTCOR) The refresh time constant register (RTCOR) specifies the upper-limit value of RTCNT. The values of RTCOR and RTCNT (lower 8 bits) are constantly compared. When the values match, the compare match flag (CMF) in RTCSR is set and RTCNT is cleared to 0. When the refresh bit (RFSH) in the individual memory control register (MCR) is set to 1 and the refresh mode is set to auto refresh, a memory refresh cycle occurs when the CMF bit is set.
Bit: Initial value: R/W: — — — — — — Bit: Initial value: R/W: 10.2.12 Cautions on Accessing Refresh Control Related Registers RFCR, RTCSR, RTCNT, and RTCOR require that a specific code be appended to the data when it is written to prevent data from being mistakenly overwritten by program overruns or other write operations (figure 10.5).
10.2.13 MCS0 Control Register (MCSCR0) The MCS0 control register (MCSCR0) is a 16-bit readable/writable register that specifies the MCS[0] pin output conditions. MCSCR0 is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
10.2.14 MCS1 Control Register (MCSCR1) The MCS1 control register (MCSCR1) specifies the MCS[1] pin output conditions. The bit configuration and functions are the same as those of MCSCR0. 10.2.15 MCS2 Control Register (MCSCR2) The MCS2 control register (MCSCR2) specifies the MCS[2] pin output conditions. The bit configuration and functions are the same as those of MCSCR0.
Endian/Access Size and Data Alignment The SH7709S supports both big endian, in which the 0 address is the most significant byte in the byte data, and little endian, in which the 0 address is the least significant byte. Switching between the two is designated by an external pin (MD5 pin) at the time of a power-on reset.
Table 10.8 16-Bit External Device/Big-Endian Access and Data Alignment Data Bus Strobe Signals W W W W E E E E 3 3 3 3 , W W W W E E E E 2 2 2 2 , W W W W E E E E 1 1 1 1 , W W W W E E E E 0 0 0 0 , D31–...
Table 10.9 8-Bit External Device/Big-Endian Access and Data Alignment Data Bus Strobe Signals W W W W E E E E 3 3 3 3 , W W W W E E E E 2 2 2 2 , W W W W E E E E 1 1 1 1 , W W W W E E E E 0 0 0 0 , D31–...
Table 10.10 32-Bit External Device/Little-Endian Access and Data Alignment Data Bus Strobe Signals W W W W E E E E 3 3 3 3 , W W W W E E E E 2 2 2 2 , W W W W E E E E 1 1 1 1 , W W W W E E E E 0 0 0 0 , Operation D31–D24...
Table 10.12 8-Bit External Device/Little-Endian Access and Data Alignment Data Bus Strobe Signals W W W W E E E E 3 3 3 3 , W W W W E E E E 2 2 2 2 , W W W W E E E E 1 1 1 1 , W W W W E E E E 0 0 0 0 , D31–...
10.3.2 Description of Areas Area 0: Area 0 physical address bits A28–A26 are 000. Address bits A31–A29 are ignored and the address range is H'00000000 + H'20000000 n – H'03FFFFFF + H'20000000 n (n 0–6 and n 1–6 are the shadow spaces). Ordinary memories such as SRAM, ROM, and burst ROM can be connected to this space.
Page 310
Area 3: Area 3 physical address bits A28–A26 are 011. Address bits A31–A29 are ignored and the address range is H'0C000000 + H'20000000 n – H'0FFFFFFF + H'20000000 n (n 0–6 and n 1–6 are the shadow spaces). Ordinary memories such as SRAM and ROM, as well as synchronous DRAM, can be connected to this space.
Page 311
When the area 5 space is accessed and ordinary memory is connected, the CS5 signal is asserted. The RD signal that can be used as OE and the WE0–WE3 signals for write control are also asserted. When the PCMCIA interface is used, the CE1A signal, CE2A signal, RD signal as OE signal, and WE1 signal are asserted.
10.3.3 Basic Interface Basic Timing: The basic interface of the SH7709S uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. Figure 10.6 shows the basic timing of normal space accesses. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle.
Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. For details, see section 10.2.4, Wait State Control Register 2 (WCR2).
Page 318
When software wait insertion is specified by WCR2, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 10.11. A 2-cycle wait is specified as a software wait. Sampling is performed at the transition from the Tw state to the T state;...
Wait states inserted by WAIT signal CKIO A25 to A0 RD/WR Read D31 to D0 Write D31 to D0 WAIT Figure 10.11 Basic Interface Wait State Timing (Wait State Insertion by W W W W A A A A I I I I T T T T Signal WAITSEL = 1) Rev.
I :B = 1:1. With the SH7709S, burst length 1 burst read/single write mode is supported as the synchronous DRAM operating mode. A data bus width of 16 or 32 bits can be selected. A 16-bit burst transfer is performed in a cache fill/write-back cycle, and only one access is performed in a write-through area write or a non-cacheable area read/write.
64M synchronous DRAM (1M × 16-bit × 4-bank) SH7709S CKI0 RAS3x CASx RD/WR DQ15 DQMUU DQMU DQMUL DQML DQMLU DQMLL DQ15 DQMU Note : "x" is U or L DQML Figure 10.12 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width)
Connection should therefore be made in the following order: with a 32-bit bus width, connect pin A0 of the synchronous DRAM to pin A2 of the SH7709S, then connect pin A1 to pin A3; with a 16-bit bus width, connect pin A0 of the synchronous DRAM to pin A1 of the SH7709S, then connect pin A1 to pin A2.
DRAM; no new access command can be issued to the same bank during this cycle, but access to synchronous DRAM for another area is possible. In the SH7709S, the number of Tpc cycles is determined by the TPC bit specification in MCR, and commands cannot be issued for the same synchronous DRAM during this interval.
independently for areas 2 and 3 by means of bits A2W1 and A2W0 or A3W1 and A3W0 in WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles. Tc2/Td1 Tc3/Td2 Tc4/Td3 CKIO A25 to A16, A15, A14, A11 to A0 CS2 or CS3...
Figure 10.15 shows the burst read timing when RCD is set to 1, A3W1 and A3W0 are set to 10, and TPC is set to 1. The BS cycle, which is asserted for one cycle at the start of a bus cycle for normal access space, is asserted in each of cycles Td1–Td4 in a synchronous DRAM cycle.
Single Read: Figure 10.16 shows the timing when a single address read is performed. As the burst length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed.
Page 329
Burst Write: The timing chart for a burst write is shown in figure 10.17. In the SH7709S, a burst write occurs only in the event of cache write-back or 16-byte DMAC transfer. In a burst write operation, following the Tr cycle in which ACTV command output is performed, a WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and a WRITA command that performs auto- precharge is issued in the Tc4 cycle.
(Trwl) (Tpc) CKIO Address upper bits A12, A11, A10 or A9 Address lower bits RD/WR RAS3x CASx DQMxx D31 to D0 (read) Figure 10.17 Basic Timing for Synchronous DRAM Burst Write Rev. 5.00, 09/03, page 286 of 760...
Page 331
Single Write: The basic timing chart for write access is shown in figure 10.18. In a single write operation, following the Tr cycle in which ACTV command output is performed, a WRITA command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data is output at the same time as the write command.
(Trwl) (Tpc) CKIO Address upper bits A12 or A10 Address lower bits RD/WR RAS3x CASx DQMxx D31 to D0 Figure 10.18 Basic Timing for Synchronous DRAM Single Write Rev. 5.00, 09/03, page 288 of 760...
Page 333
Bank Active: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, read/write command accesses are performed using commands without auto-precharge (READ, WRIT). In this case, precharging is not performed when the access ends.
Page 334
A Tnop cycle, in which no operation is performed, is inserted before the Tc cycle in which the READ command is issued in figure 10.20, but when synchronous DRAM is read, there is a two- cycle latency for the DQMxx signal that performs the byte specification. If the Tc cycle were performed immediately, without inserting a Tnop cycle, it would not be possible to perform the DQMxx signal specification for Td1 cycle data output.
CKIO A25 to A16, A13 (A25 to A16, A11) A12 (A10) A15, A14, A11 to A0 (A15 to A12, A9 to A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 Figure 10.24 Burst Write Timing (Different Row Addresses) Rev.
Page 341
Refreshing: The bus state controller is provided with a function for controlling synchronous DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1.
RTCNT cleared to 0 when RTCOR value RTCNT = RTCOR RTCNT Time H'00000000 ≠ 000 RTCSR.CKS(2 to 0) = 000 CMF flag cleared by start of refresh cycle External bus Auto-refresh cycle Figure 10.25 Auto-Refresh Operation Rev. 5.00, 09/03, page 298 of 760...
Page 344
After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the SH7709S’s standby function, and is maintained even after recovery from standby mode other than through a power-on reset. In case of a power-on reset, the bus state controller’s registers are initialized, and therefore the self-refresh state is cleared.
(driven low). Therefore, normal refreshing can be performed by having the IRQOUT pin monitored by a bus master other than the SH7709S requesting the bus, or the bus arbiter, and returning the bus to the SH7709S. When refreshing is started, and if no other interrupt request has been generated, the IRQOUT pin is negated (driven high).
Page 346
To set burst read/single write, CAS latency 1 to 3, wrap type = sequential, and burst length 1 supported by the SH7709S, arbitrary data is written in a byte-size access to the following addresses.
Before mode register setting, a 100 s idle time (depending on the memory manufacturer) must be guaranteed after powering on requested by the synchronous DRAM. If the reset signal pulse width is greater than this idle time, there is no problem in performing mode register setting immediately. The number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed.
10.3.5 Burst ROM Interface Setting bits A0BST1–0, A5BST1–0, and A6BST1–0 in BCR1 to a non-zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed access to ROM that has a nibble access function. The timing for nibble access to burst ROM is shown in figure 10.29.
CKIO A25 to A4 A3 to A0 RD/WR D31 to WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 10.29 Burst ROM Wait Access Timing Rev. 5.00, 09/03, page 305 of 760...
CKIO A25 to A4 A3 to A0 RD/WR D31 to D0 WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 10.30 Burst ROM Basic Access Timing Rev. 5.00, 09/03, page 306 of 760...
10.3.6 PCMCIA Interface In the SH7709S, setting the A5PCM bit in BCR1 to 1 makes the bus interface for physical space area 5 an IC memory card and I/O card interface as stipulated in JEIDA version 4.2 (PCMCIA2.1). Setting the A6PCM bit to 1 makes the bus interface for physical space area 6 an IC memory card and I/O card interface as stipulated in JEIDA version 4.2.
A24 to A0 A25 to A0 D15 to D0 D7 to D0 RD/WR CE1B/(CS6) D15 to D0 CE1A/(CS5) CE2B CE2A D15 to D8 PC card (memory/IO) SH7709S WE/PGM ICIORD (IORD) ICIOWR (IOWR) WAIT WAIT IOIS16 (IOIS16) Card CD1, CD2 detection...
Page 353
(CS5, CE2A, CS6, CE2B), and write data (D15–D0) in a write cycle, become insufficient with respect to RD and WR (the WE pin in the SH7709S). The SH7709S provides for this by enabling setup and hold times to be set for physical space areas 5 and 6 in the PCR register.
Memory Card Interface Burst Timing: In the SH7709S, when the IC memory card interface is selected, page mode burst access mode can be used, for read access only, by setting bits A5BST1 and A5BST0 in BCR1 for physical space area 5, or bits A6BST1 and A6BST0 in BCR1 for area 6.
When the entire 32-Mbyte memory space is used as IC memory card interface space, the common memory/attribute memory switching signal REG is generated using a port, etc. If 16 Mbytes or less of memory space is sufficient, using 16 Mbytes of memory space as common memory space and 16 Mbytes as attribute memory space enables the A24 pin to be used for the REG signal.
Page 359
I/O Card Interface Timing: Figures 10.37 and 10.38 show the timing for the PCMCIA I/O card interface. Switching between the I/O card interface and the IC memory card interface is performed according to the accessed address. When PCMCIA is designed for physical space area 5, the bus access is automatically performed as an I/O card interface access when a physical address from H'16000000 to H'17FFFFFF is accessed.
SH7709S performs a write access after a read access to physical space area n. If there is originally space between accesses, the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles.
See Appendix A.1, Pin States, for the pin states when the bus is released. The SH7709S sometimes needs to retrieve a bus it has released. For example, when memory generates a refresh request or an interrupt request internally, the SH7709S must perform the appropriate processing.
10.3.9 Bus Pull-Up With the SH7709S, address pin pull-up can be performed when the bus is released by setting the PULA bit in BCR1 to 1. The address pins are pulled up for a 4-clock period after BACK is asserted. Figure 10.41 shows the address pin pull-up timing. Similarly, data pin pull-up can be performed by setting the PULD bit in BCR1 to 1.
10.3.10 M M M M C C C C S S S S [ [ [ [ 0 0 0 0 ] ] ] ] to M M M M C C C C S S S S [ [ [ [ 7 7 7 7 ] ] ] ] Pin Control The SH7709S is provided with pins MCS[0]–MCS[7] as dedicated CS pins for the ROM connected to area 0 or 2.
Table 10.15 MCSCRx Settings and M M M M C C C C S S S S [ [ [ [ x x x x ] ] ] ] Assertion Conditions (x: 0–7) M M M M C C C C S S S S [ [ [ [ x x x x ] ] ] ] Assertion Conditions MCSCRx Settings C C C C S S S S 0 0 0 0 C C C C S S S S 2 2 2 2...
Page 369
M M M M C C C C S S S S [ [ [ [ x x x x ] ] ] ] Assertion Conditions MCSCRx Settings C C C C S S S S 0 0 0 0 C C C C S S S S 2 2 2 2 CS2/0 CAP1 CAP0 A25 Address Bus A[25:0]...
11.1 Overview The SH7709S includes a four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, memory-mapped external devices, and on-chip peripheral modules (IrDA, SCIF, A/D converter, and D/A converter).
Page 372
Channel 3: In this channel, direct address mode or indirect address transfer mode can be specified. Reload function: The value that was specified in the source address register can be automatically reloaded every four DMA transfers. This function is only available in channel 2. Transfer requests External request (From two DREQ pins (channels 0 and 1 only).
11.1.2 Block Diagram Figure 11.1 shows a block diagram of the DMAC. DMAC module Iteration SARn control Register DARn control On-chip DMATCRn peripheral Start-up module control CHCRn DMAOR DREQ0, DREQ1 IrDA, SCIF Request A/D converter priority control DEIn DACK0, DACK1 DRAK0, DRAK1 External Bus interface...
11.1.3 Pin Configuration Table 11.1 shows the DMAC pins. Table 11.1 DMAC Pins Channel Name Symbol Function DREQ0 DMA transfer request DMA transfer request input from external device to channel 0 DMA transfer request DACK0 Strobe output to an external I/O upon acceptance DMA transfer request from external device to channel 0...
11.1.4 Register Configuration Table 11.2 summarizes the DMAC registers. The DMAC has a total of 17 registers: each channel has four registers, and one overall DMAC control register. Table 11.2 DMAC Registers Abbrevi- Register Access Channel Name ation Initial Value Address Size Size 16, 32 *...
11.2 Register Descriptions 11.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) DMA source address registers 0–3 (SAR0–SAR3) are 32-bit readable/writable registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. To transfer data in 16 bits or in 32 bits, specify a 16-bit or 32-bit address boundary address.
11.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. These registers include a count function, and during a DMA transfer, these registers indicate the next destination address. To transfer data in 16-bit or 32-bit units, make sure to specify a destination address with a 16-byte boundary (16n address).
11.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 24-bit readable/writable registers that specify the DMA transfer count (bytes, words, or longwords). The number of transfers is 1 when the setting is H'000001, and 16,777,216 (the maximum) when H'000000 is set. During a DMA transfer, these registers indicate the remaining number of transfers.
11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) DMA channel control registers 0–3 (CHCR0–CHCR3) are 32-bit readable/writable registers that specify the operation mode, transfer method, etc., for each channel. Bit 20 is only used in CHCR3; it is not used in CHCR0 to CHCR2. Consequently, writing to this bit is invalid in CHCR0 to CHCR2;...
Page 381
Bits 31 to 21—Reserved: These bits are always read as 0. The write value should always be 0. Bit 20—Direct/Indirect Selection (DI): Selects direct address mode or indirect address mode in channel 3. This bit is only valid in CHCR3. Writing to this bit is invalid in CHCR0 to CHCR2; 0 is read if this bit is read.
Page 382
Bit 17—Acknowledge Mode Bit (AM): Specifies whether DACK is output in the data read cycle or in the data write cycle in dual address mode. DACK is always output in single address mode, regardless of this bit specification. This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and CHCR3;...
Page 383
Bits 13 and 12—Source Address Mode Bits 1 and 0 (SM1, SM0): Select whether the DMA source address is incremented, decremented, or left fixed. Bit 13: SM1 Bit 12: SM0 Description Fixed source address (Initial value) Source address is incremented (+1 in 8-bit transfer, +2 in 16- bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) Source address is decremented (–1 in 8-bit transfer, –2 in 16- bit transfer, –4 in 32-bit transfer;...
Page 384
Bits 11 to 8—Resource Select Bits 3 to 0 (RS3 to RS0): Specify which transfer requests will be sent to the DMAC. Bit 11: Bit 10: Bit 9: Bit 8: Description External request * , dual address mode (Initial value) Setting prohibited External request / Single address mode External address space...
Page 385
Bit 6—D D D D R R R R E E E E Q Q Q Q Select Bit (DS): Selects low-level or falling-edge detection as the sampling method for the DREQ pin used in external request mode. This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and CHCR3;...
Page 386
Bit 1—Transfer End Bit (TE): Set to 1 on completion of the number of data transfers specified in DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated. If data transfer ends due to an NMI interrupt, a DMAC address error, or clearing of the DE bit or the DME bit in DMAOR before this bit is set to 1, this bit will not be set to 1.
11.2.5 DMA Operation Register (DMAOR) The DMA operation register (DMAOR) is a 16-bit readable/writable register that controls the DMAC transfer mode. These register values are initialized to 0 in a reset. The previous value is retained in standby mode. Bit: —...
Page 388
Bit 2—Address Error Flag Bit (AE): Indicates that an address error occurred by the DMAC. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to this bit. This bit can only be cleared by writing 0 after reading 1. Bit 2: AE Description No DMAC address error;...
11.3 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip module request.
Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1 and AE, NMIF, TE = 0? Transfer request?* Bus mode, transfer request mode, DREQ detection selection system Transfer (1 transfer unit); 1 → DMATCR, DMATCR SAR and DAR updated AE = 1 or NMIF = 1 or DMATCR = 0?
11.3.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip module request.
request signal. The source of the transfer request does not have to be the data transfer source or destination. When RXI is set as the transfer request, however, the transfer source must be the SCI's receive data register (RDR). Likewise, when TXI is set as the transfer request, the transfer source must be the SCI's transmit data register (TDR).
11.3.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. Two modes (fixed mode and round-robin mode) are selected by priority bits PR1 and PR0 in the DMA operation register (DMAOR). Fixed Mode: In these modes, the priority order of the channels remain fixed.
(1) When channel 0 transfers Initial priority order Channel 0 becomes lowest- priority. Priority order after transfer (2) When channel 1 transfers Channel 1 becomes lowest- Initial priority order priority. The priority of channel 0, which was higher than channel 1, is also shifted.
Figure 11.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously for channels 0 and 3. 2.
11.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 11.5. Dual address mode has a direct address mode and indirect address mode. In direct address mode, an output address value is the data transfer target address; in indirect address mode, the value stored in the output address, not the output address value itself, is the data transfer target address.
(1) In direct address transfer mode, DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the transfer between external memories as shown in figure 11.5, data is read to the DMAC from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle.
CKIO Transfer source Transfer destination A25 to A0 address address D31 to D0 DACKn Data read cycle Data write cycle (1st cycle) (2nd cycle) Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn. Figure 11.6 Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode (Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory) (2) In indirect address transfer mode, the address of memory in which data to be transferred is...
SAR3 Memory DAR3 Transfer source module Temporary buffer Transfer destination Data buffer module When the value in SAR3 is an address, the memory data is read and the value is stored in the temporary buffer. The value to be read must be 32 bits since it is used for the address.
CKIO Transfer Transfer Transfer Indirect A25 to A0 source source destination address address (H) address (L) address Indirect Indirect Transfer Transfer D31 to D0 address (H) address (L) data data Internal Transfer source Indirect address address address Internal Transfer Transfer Transfer source address data bus data...
DACK shown in figure 11.9, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. External address bus External data bus SH7709S External DMAC memory External device...
CKIO Address output to external memory space A25 to A0 Write strobe signal to external memory space D31 to D0 Data output from external device with DACK DACKn DACK signal (active-low) to external device with DACK (a) External device with DACK external memory space (ordinary memory) CKIO Address output to external memory space...
CKIO A25 to A0 Transfer source address D31 to D0 DACKn Figure 11.11 Example of DMA Transfer Timing in Single Address Mode (16-byte Transfer, External Memory Space (Ordinary Memory) External Device with DACK) Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode in the TM bits of CHCR0–CHCR3.
DREQ Bus returned to CPU Bus cycle DMAC DMAC CPU DMAC DMAC CPU Read Write Read Write Figure 11.12 Example of DMA Transfer in Cycle-Steal Mode Burst Mode Once the bus is obtained, the transfer is performed continuously until the transfer end condition is satisfied.
Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 11.6 shows the relationship between request modes and bus modes by DMA transfer category. Table 11.6 Relationship between Request Modes and Bus Modes by DMA Transfer Category Address Request Transfer Usable...
Bus Mode and Channel Priority Order: When, for example, channel 1 is transferring in burst mode and there is a transfer request to channel 0, which has higher priority, the channel 0 transfer will begin immediately. At this time, if the priority is set in the fixed mode (CH0 > CH1), the channel 1 transfer will continue when the channel 0 transfer has completely finished, even if channel 0 is operating in cycle-steal mode or burst mode.
Number of Bus Cycle States and D D D D R R R R E E E E Q Q Q Q Pin Sampling Timing 11.3.5 Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master.
Page 408
Burst Mode, Level Detection In the case of burst mode with level detection, the DREQ sampling timing is the same as in cycle-steal mode. For example, in figure 11.20, DMAC transfer begins, at the earliest, three cycles after the first sampling is performed.
11.3.6 Source Address Reload Function Channel 2 includes a reload function, in which the value is returned to the value set in the source address register (SAR2) every four transfers by setting the RO bit in CHCR2 to 1. 16-byte transfer cannot be used.
Internal SAR2 DAR2 SAR2+2 DAR2 SAR2+4 DAR2 SAR2+6 DAR2 SAR2 address bus Internal SAR2 data SAR2+2 data SAR2+4 data SAR2+6 data data bus First transfer on channel 2 Second transfer Third transfer Fourth transfer Fifth transfer SAR2 output SAR2+2 output SAR2+4 output SAR2+6 output DAR2 output...
11.3.7 DMA Transfer Ending Conditions The DMA transfer ending conditions are different for ending on an individual channel and ending on all channels together. At the end of transfer, the following conditions are applied except in the case where the value set in the DMA transfer count register (DMATCR) reaches 0. (a) Cycle-steal mode (external request, internal request, and auto-request) When the transfer ending conditions are satisfied, DMAC transfer request acceptance is suspended.
Page 419
Conditions for Ending on All Channels Simultaneously: Transfers on all channels end (1) when the AE or NMIF (NMI flag) bit is set to 1 in DMAOR, or (2) when the DME bit in DMAOR is cleared to 0. Transfer ending when the NMIF bit is set to 1 in DMAOR: When an NMI interrupt occurs, the AE or NMIF bit is set to 1 in DMAOR and all channels stop their transfers according to the conditions in (a) to (d) described above, and pass the bus to an other bus master.
11.4 Compare Match Timer (CMT) 11.4.1 Overview The DMAC has an on-chip compare match timer (CMT) to generate DMA transfer requests. The CMT has a 16-bit counter. Features The CMT has the following features: Four types of counter input clock can be selected One of four internal clocks (P /4, P /8, P /16, P /64) can be selected.
Register Configuration Table 11.7 summarizes the CMT register configuration. Table 11.7 Register Configuration Initial Access Size Name Abbreviation Value Address (Bits) Compare match timer start CMSTR R/(W) H'0000 H'04000070 8, 16, 32 (H'A4000070) * register R/(W) * Compare match timer CMCSR0 H'0000 H'04000072...
Page 422
Bit 0—Count Start 0 (STR0): Selects whether to operate or halt CMCNT0. Bit 0: STR0 Description CMCNT0 count operation halted (Initial value) CMCNT0 count operation Compare Match Timer Control/Status Register 0 (CMCSR0) The compare match timer control/status register 0 (CMCSR0) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the clock used for incrementation.
Page 423
Bit 6—Reserved: This bit can be read or written. The wite value should always be 0. Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): Select the clock input to CMCNT from among the four internal clocks obtained by dividing the system clock (P ). When the STR bit in CMSTR is set to 1, CMCNT0 begins incrementing on the clock selected by CKS1 and CKS0.
Compare Match Constant Register 0 (CMCOR0) Compare match constant register 0 (CMCOR0) is a 16-bit register that sets the CMCNT0 compare match period. CMCOR0 is initialized to H'FFFF by a reset, but retains its previous value in standby mode. Bit: Initial value: R/W: Bit:...
CMCNT0 Count Timing One of four clocks (P /4, P /8, P /16, P /64) obtained by dividing the P clock can be selected with the CKS1 and CKS0 bits in CMCSR0. Figure 11.26 shows the timing. Internal clock CMCNT0 input clock CMCNT0 Figure 11.26 Count Timing...
CMCNT0 input clock CMCNT0 CMCOR0 Compare match signal Figure 11.27 CMF Setting Timing Compare Match Flag Clearing Timing The CMF bit in the CMCSR0 register is cleared by writing 0 to it after reading 1. Figure 11.28 shows the timing when the CMF bit is cleared by the CPU. CMCSR0 write cycle Figure 11.28 Timing of CMF Clearing by the CPU Rev.
11.5 Examples of Use 11.5.1 Example of DMA Transfer between On-Chip IrDA and External Memory In this example, receive data of the on-chip IrDA is transferred to external memory using DMAC channel 3. Table 11.8 shows the transfer conditions and register settings. In addition, it is recommended that the trigger for the number of receive FIFO data bytes in IrDA be set to 1 (RTRG1 = RTRG0 = 0 in SCFCR).
11.5.2 Example of DMA Transfer between A/D Converter and External Memory In this example, DMA transfer is performed between the on-chip A/D converter (transfer source) and the external memory (transfer destination) with the address reload function on. Table 11.9 shows the transfer conditions and register settings. Table 11.9 Transfer Conditions and Register Settings for Transfer between On-Chip A/D Converter and External Memory Transfer Conditions...
As a result, the values in the DMAC are as shown in table 11.10 when the fourth transfer ends, depending on whether the address reload function is on or off. Table 11.10 Values in DMAC after End of Fourth Transfer Items Address reload on Address reload off...
Table 11.11 Transfer Conditions and Register Settings for Transfer between External Memory and SCIF Transmitter Transfer Conditions Register Setting Transfer source: External memory SAR3 H'00400000 Value stored in address H'00400000 — H'00450000 Value stored in address H'04500000 — H'55 Transfer destination: On-chip SCIF TDR2 DAR3 H'04000156 Number of transfers: 10...
11.6 Usage Notes 1. The DMA channel control registers (CHCR0–CHCR3) can be accessed with any data size. The DMA operation register (DMAOR) must be accessed by byte (8 bits) or word (16 bits); other registers must be accessed by word (16 bits) or longword (32 bits). 2.
All channels can operate when the SH7709S is in standby mode: When the RTC output clock is being used as the counter input clock, the SH7709S is still able to count in standby mode. Synchronized read: TCNT is a sequentially changing 32-bit register. Since the peripheral module used has an internal bus width of 16 bits, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read.
12.2 TMU Registers 12.2.1 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that selects whether to use the external TCLK pin as an external clock or an input capture control usage input pin, or an output pin for the on-chip RTC output clock.
Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0. Bit 2—Counter Start 2 (STR2): Selects whether to run or halt timer counter 2 (TCNT2). Bit 2: STR2 Description TCNT2 count halted (Initial value) TCNT2 counts Bit 1—Counter Start 1 (STR1): Selects whether to run or halt timer counter 1 (TCNT1).
Page 439
Bit 8—Underflow Flag (UNF): Status flag that indicates occurrence of a TCNT underflow. Bit 8: UNF Description TCNT has not underflowed Clearing condition: When 0 is written to UNF (Initial value) TCNT has underflowed Setting condition: When TCNT underflows * Note: * Contents do not change when 1 is written to UNF.
Page 440
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): Select the external clock edge when the external clock is selected, or when the input capture function is used. Bit 4: CKEG1 Bit 3: CKEG0 Description Count/capture register set on rising edge (Initial value) Count/capture register set on falling edge Count/capture register set on both rising and falling edge...
12.2.4 Timer Constant Registers (TCOR) The TMU has three TCOR registers, one for each channel. TCOR specifies the value for setting in TCNT when a TCNT count-down results in an under flow. TCOR is a 32-bit readable/writable register. TCOR is initialized to H'FFFFFFFF by a power-on reset or manual reset, but is not initialized, and retains its contents, in standby mode.
Page 442
Because the internal bus for the SH7709S on-chip peripheral modules is 16 bits wide, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. Since TCNT counts sequentially, this time lag can create discrepancies between the data in the upper and lower halves.
12.2.6 Input Capture Register (TCPR2) Input capture register 2 (TCPR2) is a read-only 32-bit register provided only in timer 2. Control of TCPR2 setting conditions due to the TCLK pin is affected by the input capture function bits (ICPE1/ICPE0 and CKEG1/CKEG0) in TCR2. When a TCPR2 setting indication due to the TCLK pin occurs, the value of TCNT2 is copied into TCPR2.
12.3 TMU Operation Each of three channels has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). TCNT counts down. The auto-reload function enables cycle counting and counting by external events. Channel 2 has an input capture function. 12.3.1 General Operation When the STR0–STR2 bits in the timer start register (TSTR) are set to 1, the corresponding timer...
Select operation Select counter clock Set underflow interrupt generation When using input capture function Set interrupt generation Set timer constant register Initialize timer counter Start counting Note: When an interrupt has been generated, clear the flag in the interrupt handler that caused it.
Auto-Reload Count Operation: Figure 12.3 shows the TCNT auto-reload operation. TCOR value set to TCNT value TCNT during underflow TCOR H'00000000 Time STR0 STR2 Figure 12.3 Auto-Reload Count Operation TCNT Count Timing: Internal Clock Operation: Set the TPSC2–TPSC0 bits in TCR to select whether peripheral module clock P or one of the four internal clocks created by dividing it is used (P /4, P /16, P /64, P /256).
External Clock Operation: Set the TPSC2–TPSC0 bits in TCR to select the external clock (TCLK) as the timer clock. Use the CKEG1 and CKEG0 bits in TCR to select the detection edge. Rising, falling, or both edges may be selected. The pulse width of the external clock must be at least 1.5 peripheral module clock cycles for single edges or 2.5 peripheral module clock cycles for both edges.
TCOR value set to TCNT value TCNT during underflow TCOR H'00000000 Time TCLK TCPR2 Set TCNT value ICPI Figure 12.7 Operation Timing when Using Input Capture Function (Using TCLK Rising Edge) 12.4 Interrupts There are two sources of TMU interrupts: underflow interrupts (TUNI) and interrupts when using the input capture function (TICPI2).
12.4.2 Status Flag Clearing Timing The status flag can be cleared by writing 0 from the CPU. Figure 12.9 shows the timing. TCR write cycle Peripheral address bus TCR address UNF, ICPF Figure 12.9 Status Flag Clearing Timing 12.4.3 Interrupt Sources and Priorities The TMU produces underflow interrupts for each channel.
12.5 Usage Notes 12.5.1 Writing to Registers Synchronization processing is not performed for timer counting during register writes. When writing to registers, always clear the appropriate start bits for the channel (STR2–STR0) in the timer start register (TSTR) to halt timer counting. 12.5.2 Reading Registers Synchronization processing is performed for timer counting during register reads.
Section 13 Realtime Clock (RTC) 13.1 Overview The SH7709S has a realtime clock (RTC) with its own 32.768-kHz crystal oscillator. 13.1.1 Features Clock and calendar functions (BCD display): Seconds, minutes, hours, date, day of the week, month, and year 1-Hz to 64-Hz timer (binary display)
13.2 RTC Registers 13.2.1 64-Hz Counter (R64CNT) The 64-Hz counter (R64CNT) is an 8-bit read-only register that indicates the states of the RTC divider circuit, RTC prescaler, and R64CNT between 64 Hz and 1 Hz. R64CNT is initialized to H'00 by setting the RESET bit in RTC control register 2 (RCR2) or the ADJ bit in RCR2 to 1.
13.2.3 Minute Counter (RMINCNT) The minute counter (RMINCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded minute section of the RTC. The count operation is performed by a carry for each minute of the second counter. The range that can be set is 00–59 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2.
13.2.5 Day of Week Counter (RWKCNT) The day of week counter (RWKCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded day of week section of the RTC. The count operation is performed by a carry for each day of the date counter. The range that can be set is 0–6 (decimal).
13.2.6 Date Counter (RDAYCNT) The date counter (RDAYCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded date section of the RTC. The count operation is performed by a carry for each day of the hour counter. The range that can be set is 01–31 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2.
13.2.8 Year Counter (RYRCNT) The year counter (RYRCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded year section of the RTC. The least significant 2 digits of the western calendar year are displayed. The count operation is performed by a carry for each year of the month counter. The range that can be set is 00–99 (decimal).
13.2.10 Minute Alarm Register (RMINAR) The minute alarm register (RMINAR) is an 8-bit readable/writable register, and an alarm register corresponding to the BCD-coded minute section counter RMINCNT of the RTC. When the ENB bit is set to 1, a comparison with the RMINCNT value is performed. From among the RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated.
13.2.12 Day of Week Alarm Register (RWKAR) The day of week alarm register (RWKAR) is an 8-bit readable/writable register, and an alarm register corresponding to the BCD-coded day of week section counter RWKCNT of the RTC. When the ENB bit is set to 1, a comparison with the RWKCNT value is performed. From among the RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated.
13.2.13 Date Alarm Register (RDAYAR) The date alarm register (RDAYAR) is an 8-bit readable/writable register, and an alarm register corresponding to the BCD-coded date section counter RDAYCNT of the RTC. When the ENB bit is set to 1, a comparison with the RDAYCNT value is performed. From among the registers RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated.
13.2.15 RTC Control Register 1 (RCR1) The RTC control register 1 (RCR1) is an 8-bit readable/writable register that affects carry flags and alarm flags. It also selects whether to generate interrupts for each flag. Because flags are sometimes set after an operand read, do not use this register in read-modify-write processing. RCR1 is initialized to H'00 by a power-on reset or a manual reset.
Bit 3—Alarm Interrupt Enable Flag (AIE): When the alarm flag (AF) is set to 1, the AIE bit allows interrupts. Bit 3: AIE Description An alarm interrupt is not generated when the AF flag is set to 1 (Initial value) An alarm interrupt is generated when the AF flag is set to 1 Bit 0—Alarm Flag (AF): The AF flag is set to 1 when the alarm time set in an alarm register (only registers with ENB bit set to 1) matches the clock and calendar time.
Page 465
Bits 6 to 4—Periodic Interrupt Flags (PES2-PES0): Specify the periodic interrupt. Bit 6: PES2 Bit 5: PES1 Bit 4: PES0 Description No periodic interrupts generated (Initial value) Periodic interrupt generated every 1/256 second Periodic interrupt generated every 1/64 second Periodic interrupt generated every 1/16 second Periodic interrupt generated every 1/4 second Periodic interrupt generated every 1/2 second Periodic interrupt generated every 1 second...
Bit 0—Start Bit (START): Halts and restarts the counter (clock). Bit 0: START Description Second/minute/hour/day/week/month/year counter halts Second/minute/hour/day/week/month/year counter runs normally (Initial value) Note: The 64-Hz counter always runs unless stopped with the RTCEN bit. 13.3 RTC Operation 13.3.1 Initial Settings of Registers after Power-On All the registers should be set after the power is turned on.
13.3.3 Reading the Time Figure 13.3 shows how to read the time. If a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. Part (a) in figure 13.3 shows the method of reading the time without using interrupts;...
13.3.4 Alarm Function Figure 13.4 shows how to use the alarm function. Alarms can be generated using seconds, minutes, hours, day of the week, date, month, or any combination of these. Set the ENB bit (bit 7) to 1 in the register to which the alarm applies, and then set the alarm time in the lower bits.
13.5. Table 13.5 Recommended Oscillator Circuit Constants (Recommended Values) fosc Cout 32.768 kHz 10 to 22 pF 10 to 22 pF SH7709S EXTAL2 XTAL2 XTAL Notes: 1. Select either the C or C side for the frequency adjustment variable capacitor according to requirements such as frequency range, degree of stability, etc.
13.4 Usage Notes 13.4.1 Register Writing during RTC Count The following RTC registers cannot be written to during an RTC count (while bit 0 = 1 in RCR2). RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, RYRCNT The RTC count must be halted before writing to any of the above registers. 13.4.2 Use of Realtime Clock (RTC) Periodic Interrupts The method of using the periodic interrupt function is shown in figure 13.6.
Section 14 Serial Communication Interface (SCI) 14.1 Overview The SH7709S has an on-chip serial communication interface (SCI) that supports both asynchronous and clock synchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. The SCI supports a smart card interface, which is a serial communication feature for IC card interfaces that conforms to the ISO/IEC standard 7816-3 for identification cards.
Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external) Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive- error interrupts are requested independently. When the SCI is not in use, it can be stopped by halting the clock supplied to it, saving power. 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the SCI.
Figures 14.2, 14.3, and 14.4 show block diagrams of the SCI I/O port pins. SCIF pin I/O and data control is performed by bits 11 to 8 of SCPCR and bits 5 and 4 of SCPDR. For details, see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR).
SCPT[0]/RxD0 Serial receive data Internal data bus PDRR* Legend PDRR: PDR read Note: * When reading the RxD0 pin, set the RE bit in SCSCR to 1. Figure 14.4 SCPT[0]/RxD0 Pin 14.1.3 Pin Configuration The SCI has the serial pins summarized in table 14.1. Table 14.1 SCI Pins Pin Name Abbreviation...
14.1.4 Register Configuration Table 14.2 summarizes the SCI internal registers. These registers select the communication mode (asynchronous or synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. Table 14.2 SCI Registers Name Abbreviation Initial Value Address Access size Serial mode register...
14.2.2 Receive Data Register (SCRDR) The receive data register (SCRDR) stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the receive shift register (SCRSR) into SCRDR for storage. SCRSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously.
14.2.4 Transmit Data Register (SCTDR) The transmit data register (SCTDR) is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in SCTDR into SCTSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in SCTDR during serial transmission from SCTSR.
Page 479
Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode. In the synchronous mode, the data length is always eight bits, regardless of the CHR setting. Bit 6: CHR Description 8-bit data (Initial value) 7-bit data * Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit data register (SCTDR) is not transmitted.
Page 480
Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because no stop bits are added. When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character.
14.2.6 Serial Control Register (SCSCR) The serial control register (SCSCR) operates the SCI transmitter/receiver, selects the serial clock output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'00 by a reset and in standby or module standby mode.
Page 482
Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter. Bit 5: TE Description Transmitter disabled * (Initial value) Transmitter enabled * Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SCSSR) is fixed at 1. 2.
Page 483
Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if SCTDR does not contain new transmit data when the MSB is transmitted. Bit 2: TEIE Description Transmit-end interrupt (TEI) requests are disabled * (Initial value) Transmit-end interrupt (TEI) requests are enabled * Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register (SCSSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit to 0, or by clearing the TEIE bit to 0.
14.2.7 Serial Status Register (SCSSR) The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate the SCI operating state. The CPU can always read and write to SCSSR, but cannot write 1 to the status flags (TDRE, RDRF, ORER, PER, and FER).
Page 485
Bit 6—Receive Data Register Full (RDRF): Indicates that SCRDR contains received data. Bit 6: RDRF Description SCRDR does not contain valid receive data (Initial value) [Clearing conditions] (1) RDRF is cleared to 0 when the chip is reset or enters standby mode. (2) Software reads RDRF after it has been set to 1, then writes 0 in RDRF.
Page 486
Bit 4—Framing Error (FER): Indicates that data reception aborted due to a framing error in asynchronous mode. Bit 4: FER Description Receiving is in progress or has ended normally * (Initial value) [Clearing conditions] (1) FER is cleared to 0 when the chip is reset or enters standby mode. (2) When software reads FER after it has been set to 1, then writes 0 to FER.
Page 487
Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, SCTDR did not contain valid data, so transmission has ended. TEND is a read-only bit and cannot be written to. Bit 2: TEND Description Transmission is in progress [Clearing condition] TEND is cleared to 0 when software reads TDRE after it has been set to 1, then...
14.2.8 SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR) The SC port control register (SCPCR) and SC port data register (SCPDR) control I/O and data for the port pins multiplexed with the serial communication interface (SCI) pins. SCPCR settings are used to perform I/O control, to enable data written in SCPDR to be output to the TxD pin, and input data to be read from the RxD pin, and to control serial transmission/reception breaks.
Page 489
SCPDR Bit 1—Serial Clock Port Data (SCP1DT): Specifies the serial port SCK pin I/O data. Input or output is specified by the SCP1MD1 and SCP1MD0 bits. In output mode, the value of the SCP1DT bit is output to the SCK pin. Bit 1: SCP1DT Description...
14.2.9 Bit Rate Register (SCBRR) The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR.
Table 14.4 lists examples of SCBRR settings in asynchronous mode, and table 14.5 lists examples of SCBRR settings in synchronous mode. Table 14.4 Bit Rates and SCBRR Settings in Asynchronous Mode P (MHz) 2.097152 2.4576 Bit Rate (bits/s) n Error ( ) n Error ( ) n Error ( ) 0.03...
Page 492
P (MHz) 4.9152 Bit Rate (bits/s) n Error ( ) n Error ( ) n Error ( ) 0.31 –0.25 –0.44 0.00 0.16 0.16 0.00 0.16 0.16 0.00 0.16 0.16 1200 0.00 0.16 0.16 2400 0.00 0.16 0.16 4800 0.00 –1.36 0.16 9600...
Table 14.6 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 14.7 and 14.8 list the maximum rates for external clock input. Table 14.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P (MHz)
14.3 Operation 14.3.1 Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Asynchronous/synchronous mode and the transmission format are selected in the serial mode register (SCSMR), as shown in table 14.9.
Table 14.9 Serial Mode Register Settings and SCI Communication Formats SCSMR Settings SCI Communication Format Bit 7 Bit 6 Bit 5 Bit 2 Bit 3 Data Parity Multipro- Stop Bit C/A A A A STOP Mode Length cessor Bit Length Asynchronous 8-bit Not set Not set...
14.3.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible.
Transmit/Receive Formats: Table 14.11 lists the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Table 14.11 Serial Communication Formats (Asynchronous Mode) SCSMR Bits Serial Transmit/Receive Format and Frame Length CHR PE STOP START...
When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 14.6 so that the rising edge of the clock occurs at the center of each transmit data bit.
Initialization Clear TE and RE bits in SCSCR to 0 Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) Select communication format in SCSMR Set value in SCBRR Wait Has a 1-bit interval elapsed? Set TE and RE bits in SCSCR to 1 and set RIE, TIE, TEIE, and MPIE bits Note: Numbers in parentheses refer to steps in the preceding procedure description.
Start of transmission Read TDRE bit in SCSSR TDRE = 1? Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 All data transmitted? Read TEND bit in SCSSR TEND = 1? Break output? Set SCPDR and SCPCR Clear TE bit in SCSCR to 0 End of transmission Note: Numbers in parentheses refer to steps in the preceding procedure description.
Page 504
In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (SCTDR) contains new data, and loads this data from SCTDR into the transmit shift register (SCTSR).
Figure 14.9 shows an example of SCI transmit operation in asynchronous mode. Start Parity Stop Parity Stop Start Data Data Serial Idle (mark) data state TDRE TEND TXI interrupt TXI interrupt TXI interrupt TEI interrupt request handler writes request request generated data to SCTDR generated...
Start of reception Read ORER, PER, and FER bits in SCSSR ORER = 1? Read RDRF bit in SCSSR Error handling RDRF = 1? Read receive data from SCRDR and clear RDRF bit in SCSSR to 0 All data received? Clear RE bit in SCSCR to 0 End of reception Note: Numbers in parentheses refer to steps in the preceding procedure description.
Page 507
Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCSCR to 0 PER = 1? Parity error handling Clear ORER, PER, and FER bits in SCSSR to 0 Figure 14.10 Sample Flowchart for Receiving Serial Data (cont) Rev.
In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. 3.
Figure 14.11 shows an example of SCI receive operation in asynchronous mode. Start Parity Stop Parity Stop Start Data Data Serial Idle (mark) data state RDRF RXI interrupt request generated 1 frame RXI interrupt handler ERI interrupt reads data and clears request generated RDRF bit to 0 by framing error...
Transmitting station Serial communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmit cycle: Data transmit cycle: specifies receiving station data transmission to...
Start of transmission Read TDRE bit in SCSSR TDRE = 1? Write transmit data to SCTDR and set MPBT bit in SCSSR Clear TDRE bit to 0 Transmission ended? Read TEND bit in SCSSR TEND = 1? Break output? Set SCPDR and SCPCR Clear TE bit SCSCR to 0 End of transmission Note: Numbers in parentheses refer to steps in the preceding procedure description.
In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (SCTDR) contains new data, and transfers this data from SCTDR into the transmit shift register (SCTSR).
Page 513
Receiving Multiprocessor Serial Data: Figure 14.15 shows a sample flowchart for receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is: 1. ID receive cycle: Set the MPIE bit in the serial control register (SCSCR) to 1. 2. SCI status check and compare to ID reception: Read the serial status register (SCSSR), check that RDRF is set to 1, then read data from the receive data register (SCRDR) and compare with the processor’s own ID.
Start of reception Set MPIE bit in SCSCR to 1 Read ORER and FER bits in SCSSR FER = 1 or ORER = 1? Read RDRF bit in SCSSR RDRF = 1? Read receive data from SCRDR Is ID the station's ID? Read ORER and FER bits in SSCSR...
Page 515
Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCSCR to 0 Clear ORER and FER bits in SCSSR to 0 Figure 14.15 Sample Flowchart for Receiving Multiprocessor Serial Data (cont) Rev.
Figure 14.16 shows an example of SCI receive operation using a multiprocessor format. Data Data Start Stop Start Stop (ID1) (data 1) Serial Idle (mark) data state MPIE RDRF value RXI interrupt request RXI interrupt handler ID is not station's No RXI interrupt (multiprocessor interrupt) reads RDR data and...
Page 517
Data Data Start Stop Stop Start (ID2) (Data 2) Serial Idle (mark) data state MPIE RDRF Data2 value RXI interrupt request RXI interrupt handler ID is that of station, MPIE bit (multiprocessor reads RDR data and so reception continues set to 1 interrupt) generated, clears RDRF bit to 0 unchanged and data...
14.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress.
Page 519
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR).
Initialization Clear TE and RE bits in SCSCR to 0 Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCSCR (TE and RE are 0) Set transmit/receive format in SCSMR Set value in SCBRR Wait Has a 1-bit period elapsed? Set TE and RE bits in SCSCR to 1 and set RIE, TIE, TEIE, and MPIE bits Note: Numbers in parentheses refer to steps in the preceding procedure description.
Start of transmission Read TDRE bit in SCSSR TDRE = 1? Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 All data transmitted? Read TEND bit in SCSSR TEND = 1? Clear TE bit in SCSCR to 0 End of transmission Note: Numbers in parentheses refer to steps in the preceding procedure description.
In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (SCTDR) contains new data and loads this data from SCTDR into the transmit shift register (SCTSR).
Page 523
Receiving Serial Data (Synchronous Mode): Figure 14.21 shows a sample flowchart for receiving serial data. When switching from asynchronous mode to synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled.
Start of reception Read ORER bit in SCSSR ORER = 1? Read RDRF bit in SCSSR Error handling RDRF = 1? Read receive data from SCRDR and clear RDRF bit in SCSSR to 0 All data received? Clear RE bit in SCSCR to 0 End of reception Note: Numbers in parentheses refer to steps in the preceding procedure description.
Page 525
Error handling ORER = 1? Overrun error handling Clear ORER bit in SCSSR to 0 Figure 14.21 Sample Flowchart for Receiving Serial Data (cont) In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2.
Transfer direction Serial clock Serial Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 data RDRF ORER ERI interrupt RXI interrupt RXI interrupt RXI interrupt request generated request request handler reads data by overrun error generated generated and clears RDRF...
Start of transmission/reception Read TDRE bit in SCSSR TDRE = 1? Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 Read ORER bit in SCSSR ORER = 1? Error processing Read RDRF bit in SCSSR RDRF = 1? Read receive data from SCRDR and clear RDRF bit in SCSSR to 0 All data...
14.4 SCI Interrupts The SCI has four interrupt sources transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI). Table 14.13 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCSCR).
14.5 Usage Notes Note the following points when using the SCI. SCTDR Writing and TDRE Flag: The TDRE bit in the serial status register (SCSSR) is a status flag indicating loading of transmit data from SCTDR into SCTSR. The SCI sets TDRE to 1 when it transfers data from SCTDR to SCTSR.
TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the TEND flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally.
Page 531
The receive margin in asynchronous mode can therefore be expressed as in equation 1. Equation 1: (1 + F) 100% M = 0.5 0.5)F Where: Receive margin ( ) Ratio of clock frequency to bit rate (N Clock duty cycle (D 0 to 1.0) L Frame length (L 9 to 12)
Section 15 Smart Card Interface 15.1 Overview As an added serial communications interface function, the SCI supports an IC card (smart card) interface that conforms to the data transfer protocol (asynchronous half-duplex character transmission protocol) of the ISO/IEC7816-3 (Identification Card) standard. Register settings are used to switch between the normal serial communication interface and the smart card interface.
15.1.2 Block Diagram Figure 15.1 shows a block diagram of the smart card interface. Internal Module data bus data bus SCBRR SCRDR SCTDR SCSCMR SCSSR SCSCR SCSMR Baud rate generator P /4 SCRSR SCTSR Transmit/ receive P /16 control P /64 Clock Parity generation Parity check...
15.2 Register Descriptions This section describes the registers added for the smart card interface and the bits whose functions are changed. 15.2.1 Smart Card Mode Register (SCSCMR) The smart card mode register (SCSCMR) is an 8-bit readable/writable register that selects smart card interface functions.
Bit 0—Smart Card Interface Mode Select (SMIF): Enables the smart card interface function. Bit 0 : SMIF Description Smart card interface function disabled (Initial value) Smart card interface function enabled 15.2.2 Serial Status Register (SCSSR) In smart card interface mode, the function of SCSSR bit 4 is changed. The setting conditions for bit 2, the TEND bit, are also changed.
Bits 3 to 0: These bits have the same function as in the ordinary SCI. See section 14, Serial Communication Interface (SCI), for more information. The setting conditions for bit 2, the transmit end bit (TEND), are changed as follows. Bit 2: TEND Description Transmission is in progress...
15.3.2 Pin Connections Figure 15.2 shows the pin connection diagram for the smart card interface. During communication with an IC card, transmission and reception are both carried out over the same data transfer line, so connect the TxD and RxD pins on the chip. Pull up the data transfer line to the power supply side with a register.
15.3.3 Data Format Figure 15.3 shows the data format for the smart card interface. In this mode, parity is checked every frame while receiving and error signals sent to the transmitting side whenever an error is detected so that data can be re-transmitted. During transmission, error signals are sampled and data re-transmitted whenever an error signal is detected.
5. The transmitting side transmits the next frame of data unless it receives an error signal. If it does receive an error signal, it returns to step 2 to re-transmit the erroneous data. 15.3.4 Register Settings Table 15.3 shows the bit map of the registers that the smart card interface uses. Bits shown as 1 or 0 must be set to the indicated value.
In the inverse convention type, the logical 1 level is state A, the logical 0 level is state Z, and communication is MSB first. The start character data is H'3F. Parity is even (from the smart card standard), and so the parity bit is 0, which corresponds to state Z. Only data bits D7–D0 are inverted by the SINV bit.
Table 15.4 Relationship of n to CKS1 and CKS0 CKS1 CKS0 Table 15.5 Examples of Bit Rate B (Bits/s) for SCBRR Settings (n P (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 9600.0 13440.9 14400.0 17473.1 19200.0 21505.4 24193.5 4800.0 6720.4 7200.0 8736.6...
Table 15.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode) P (MHz) Maximum Bit Rate (Bits/s) 7.1424 9600 10.00 13441 10.7136 14400 13.00 17473 14.2848 19200 16.00 21505 18.00 24194 The bit rate error is found as follows: Error (%) = ( 2n 1 1488 (N + 1)
15.3.6 Data Transmission and Reception Initialization: Initialize the SCI using the following procedure before sending or receiving data. Initialization is also required for switching from transmit mode to receive mode or from receive mode to transmit mode. Figure 15.5 shows a flowchart of the initialization process. 1.
Initialization Clear TE and RE bits in SCSCR to 0 Clear FER/ERS, PER and ORER flags in SCSSR to 0 Set parity in O/E bit, set clock in CKS1 and CKS0 bits, and set C/A, in SCSMR Set SMIF, SDIR, and SINV bits in SCSMR Set value in SCBRR Set clock in CKE1 and CKE0 bits,...
Page 547
Serial Data Transmission: The processing procedures in the smart card mode differ from ordinary SCI processing because data is retransmitted when an error signal is sampled during a data transmission. This results in the transmission processing flowchart shown in figure 15.6. 1.
Start Initialize Start of transmission FER/ERS = 0? Error handling TEND = 1? Write transmit data in SCTDR and clear TDRE flag in SCSSR to 0 All data transmitted? FER/ERS = 0? Error handling TEND = 1? Clear TE bit in SCSCR to 0 End of transmission Note: Numbers in parentheses refer to steps in the preceding procedure description.
Page 549
Serial Data Reception: The processing procedures in smart card mode are the same as in ordinary SCI processing. The reception processing flowchart is shown in figure 15.7. 1. Initialize the smart card interface mode as described above in Initialization and in figure 15.5. 2.
Start Initialize Start of reception ORER = 0 or PER = 0? Error handling RDRF = 1? Write receive data from SCRDR and clear RDRF flag in SCSSR to 0 All data received? Clear RE bit in SCSCR to 0 End of reception Note: Numbers in parentheses refer to steps in the preceding procedure description.
Switching Modes: When switching from receive mode to transmit mode, check that the receive operation is completed before starting initialization, clearing RE to 0, and setting TE to 1. The RDRF, PER, and ORER flags can be used to check if reception is completed. When switching from transmit mode to receive mode, check that the transmit operation is completed before starting initialization, clearing TE to 0, and setting RE to 1.
372 clock cycles 186 clock cycles 371 0 371 0 Base clock Start Receive data (RxD) Synchro- nization sampling timing Data sampling timing Figure 15.8 Receive Data Sampling Timing in Smart Card Mode The receive margin is found from the following equation: For smart card mode: M = (0.5 0.5)F...
15.4.2 Retransmission (Receive and Transmit Modes) Retransmission when SCI is in Receive Mode: Figure 15.9 shows the retransmission operation in the SCI receive mode. 1. When the received parity bit is checked and an error is found, the PER bit in SCSSR is automatically set to 1.
Retransmission when SCI is in Transmit Mode: Figure 15.10 shows the retransmission operation in the SCI transmit mode. 1. After transmission of one frame is completed, the FER/ERS bit in SCSSR is set to 1 when a error signal is returned from the receiving side. If the RIE bit in SCSCR is enabled at this time, an ERI interrupt is requested.
(SCIF) 16.1 Overview The SH7709S has a two-channel serial communication interface with FIFO (SCIF) that supports asynchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception that enable the SH7709S to perform efficient high-speed continuous communication.
Figures 16.2 to 16.4 show the SCIF I/O port pins. SCIF pin I/O and data control is performed by bits 11 to 8 of SCPCR and bits 5 and 4 of SCPDR. For details, see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR).
SCIF SCPT[4]/RxD2 Serial receive data Internal data bus PDRR* Legend PDRR: SCPDR read Note: * When reading the RxD2 pin, set the RE bit in SCSCR to 1. Figure 16.4 SCPT[4]/RxD2 Pin 16.1.3 Pin Configuration The SCIF has the serial pins summarized in table 16.1. Table 16.1 SCIF Pins Pin Name Abbreviation...
16.1.4 Register Configuration Table 16.2 summarizes the SCIF internal registers. These registers specify the data format and bit rate, and control the transmitter and receiver sections. Table 16.2 SCIF Registers Register Name Abbreviation R/W Initial Value Address Access size Serial mode register 2 SCSMR2 H'00 H'04000150...
16.2 Register Descriptions 16.2.1 Receive Shift Register (SCRSR) The receive shift register (SCRSR) receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCFRDR, the receive FIFO data register.
16.2.4 Transmit FIFO Data Register (SCFTDR) The transmit FIFO data register (SCFTDR) is a FIFO register comprising sixteen 8-bit stages that stores data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed until there is no transmit data left in SCFTDR.
Page 563
Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data. Bit 5: PE Description Parity bit not added or checked (Initial value) Parity bit added and checked * Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting.
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): Select the internal clock source of the on- chip baud rate generator. According to the setting of the CKS1 and CKS0 bits four clock sources are available. P , P /4, P /16 and P /64. For further information on the clock source, bit rate register settings, and baud rate, see section 16.2.8, Bit Rate Register (SCBRR).
Page 565
Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full (RXI) and receive-error (ERI) interrupts requested when serial receive data is transferred from the receive shift register (SCRSR) to the receive FIFO data register (SCFRDR), when the quantity of data in the receive FIFO register becomes more than the specified receive trigger number, and when the RDRF flag in SCSSR is set to1.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): Select the SCIF clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. The CKE0 setting is valid only when the SCIF is operating on the internal clock (CKE1 0).
Page 567
Bit 7—Receive Error (ER): Indicates the occurrence of a framing error, or of a parity error when receiving data that includes parity. Bit 7: ER Description Receiving is in progress or has ended normally * (Initial value) [Clearing conditions] (1) By a power-on reset or in standby mode ER is cleared to 0 when the chip is reset or enters standby mode (2) When 0 is written after 1 is read from ER A framing error or parity error has occurred *...
Page 568
Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data in SCFTDR has become less than the transmission trigger number specified by the TTRG1 and TTRG0 bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is enabled.
Page 569
Bit 3—Framing Error (FER): Indicates a framing error in the data read from the receive FIFO data register (SCFRDR). Bit 3: FER Description No receive framing error occurred in the data read from SCFRDR (Initial value) [Clearing conditions] (1) When the chip undergoes a power-on reset or enters standby mode (2) When no framing error is present in the data read from SCFRDR A receive framing error occurred in the data read from SCFRDR [Setting condition]...
Page 570
Bit 1—Receive FIFO Data Full (RDF): Indicates that receive data has been transferred to the receive FIFO data register (SCFRDR), and the quantity of data in SCFRDR has become greater than the receive trigger number specified by the RTRG1 and RTRG0 bits in the FIFO control register (SCFCR).
Upper 8 bits: PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 Initial value: R/W: Bits 15 to 12—Number of Parity Errors 3 to 0 (PER3 to PER0): Indicate the quantity of data including a parity error in the receive data stored in the receive FIFO data register (SCFRDR). The value indicated by bits 15 to 12 represents the number of parity errors in SCFRDR.
Table 16.3 SCSMR Settings SCSMR Settings Clock Source CKS1 CKS0 P /4 P /16 P /64 Note: The bit rate error is given by the following formula: Error (%) = 2n 1 (N+1) Table 16.4 lists examples of SCBRR settings. Table 16.4 Bit Rates and SCBRR Settings P (MHz) 2.097152...
Page 573
P (MHz) 3.6864 Bit Rate (bits/s) n Error ( ) n Error ( ) n Error ( ) 0.03 0.70 0.03 0.16 0.00 0.16 0.16 0.00 0.16 0.16 0.00 0.16 1200 0.16 0.00 0.16 2400 0.16 0.00 0.16 4800 –2.34 0.00 0.16 9600...
Page 574
P (MHz) 6.144 7.3728 Bit Rate (bits/s) n Error ( ) n Error ( ) n Error ( ) 0.08 –0.07 0.03 0.00 0.00 0.16 0.00 0.00 0.16 0.00 0.00 0.16 1200 0.00 0.00 0.16 2400 0.00 0.00 0.16 4800 0.00 0.00 0.16...
Table 16.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Table 16.6 list the maximum rates for external clock input. Table 16.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P (MHz) Maximum Bit Rate (bits/s)
16.2.9 FIFO Control Register (SCFCR) Bit: RTRG1 RTRG0 TTRG1 TTRG0 TFRST RFRST LOOP Initial value: R/W: The FIFO control register (SCFCR) resets the quantity of data in the transmit and receive FIFO registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU.
Page 579
Bit 3—Modem Control Enable (MCE): Enables modem control signals CTS and RTS. Bit 3: MCE Description Modem signal disabled * (Initial value) Modem signal enabled Note: * CTS is fixed at active 0 regardless of the input value, and RTS is also fixed at 0. Bit 2—Transmit FIFO Data Register Reset (TFRST): Disables the transmit data in the transmit FIFO data register and resets the data to the empty state.
16.2.10 FIFO Data Count Register (SCFDR) SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR with the lower 8 bits.
16.3 Operation 16.3.1 Overview For serial communication, the SCIF has an asynchronous mode in which characters are synchronized individually. Refer to section 14.3.2, Operation in Asynchronous Mode. The SCIF has a 16-byte FIFO buffer for both transmit and receive operations, reducing the overhead of the CPU, and enabling continuous high-speed communication.
Table 16.8 SCSCR Settings and SCIF Clock Source Selection SCSCR Settings SCIF Transmit/Receive Clock Bit 1 Bit 0 Mode CKE1 CKE0 Clock Source SCK Pin Function Asynchronous Internal SCIF does not use the SCK pin mode Outputs a clock with a frequency 16 times the bit rate External Inputs a clock with frequency 16 times the...
Page 583
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected by bits CKE1 and CKE0 in the serial control register (SCSCR) (table 16.8). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate.
Initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 Set CKE1 and CKE0 bits in SCSCR (leaving TE and RE bits cleared to 0) Set communication format in SCSMR Set value in SCBRR Wait 1-bit interval elapsed? Set RTRG1-0, TTRG1-0, and MCE...
Page 585
• Serial data transmission Figure 16.6 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. 1. SCIF status check and transmit data write: Read serial status register (SCSSR) and check that the TDFE flag is set to 1, then write transmit data to the transmit FIFO data register (SCFTDR), read 1 from the TDFE and TEND flags, then clear these flags to 0.
Start of transmission Read TDFE bit in SCSSR TDFE= 1? Write transmit data (16 - transmit trigger set number) to SCFTDR, read 1 from TDFE bit and TEND flag in SCSSR, then clear to 0 All data transmitted? Read TEND bit in SCSSR TEND= 1? Break output? Set SCPDR and SCPCR...
Page 587
In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCSSR) is set to 1 before writing transmit data to SCFTDR.
Figure 16.7 shows an example of the operation for transmission. Start Parity Stop Parity Stop Start Data Data Serial Idle (mark) data state TDFE TEND TXI interrupt Data written to TXI interrupt request SCFTDR and TDFE request flag read as 1 then cleared to 0 by TXI interrupt handler One frame...
Page 589
• Serial data reception Figures 16.9 and 16.10 show a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. 1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCSSR to identify any error, perform the appropriate error handling, then clear the DR, ER, and BRK flags to 0.
Start of reception Read ORER, PER, FER flags in SCSSR PER v FER v ORER = 1? Error handling Read RDF flag in SCSSR RDF = 1? Read receive data from SCFRDR, and clear RDF flag in SCSSR to 0 All data received? Clear RE bit in SCSCR to 0 End of reception...
1. Whether a framing error or parity error has occurred in the receive data read from SCFRDR can be ascertained from the FER and PER bits in SCSSR. 2. When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set.
Page 592
In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3.
Figure 16.11 shows an example of the operation for reception. Start Parity Stop Parity Stop Start Data Data Serial Idle (mark) D 0 D 1 D 7 0/1 data state RXI interrupt request One frame Data read and RDF ERI interrupt flag read as 1 then request generated cleared to 0 by...
16.4 SCIF Interrupts The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive-data-full (RXI), and break (BRI). Table 16.10 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE and RIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources.
16.5 Usage Notes Note the following when using the SCIF. 1. SCFTDR Writing and TDFE Flag: The TDFE flag in the serial status register (SCSSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR).
5. TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the TEND flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally.
Page 597
Equation 2: When D = 0.5 and F = 0: (0.5 – 1/(2 16)) 46.875 This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Rev. 5.00, 09/03, page 553 of 760...
Section 17 IrDA 17.1 Overview The SH7709S has an on-chip Infrared Data Association (IrDA) interface which is based on the IrDA 1.0 system and can perform infrared communication. It also can be used as the SCIF by making register settings.
17.1.2 Block Diagram Figure 17.1 shows a block diagram of the IrDA. Clock input TxD1 Modulation unit Transfer clock SCIF Demodulation unit RxD1 IrDA Switching IrDA/SCIF Legend SCIF: Serial communication interface with FIFO Figure 17.1 Block Diagram of IrDA Rev. 5.00, 09/03, page 556 of 760...
Figures 17.2 to 17.4 show the IrDA I/O port pins. SCIF pin I/O and data control is performed by bits 7 to 4 of SCPCR and bits 3 and 2 of SCPDR. For details, see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR).
IrDA SCPT[2]/RxD1 Serial receive data Internal data bus PDRR * Legend PDRR: SCPDR read Note: * When reading the RxD1 pin, set the RE bit in SCSCR to 1. Figure 17.4 SCPT[2]/RxD1 Pin 17.1.3 Pin Configuration The IrDA has the serial pins summarized in table 17.1. Table 17.1 IrDA Pins Pin Name Signal Name...
17.1.4 Register Configuration The IrDA has the internal registers shown in table 17.2. These registers select IrDA or SCIF mode, specify the data format and a bit rate, and control the transmit and receive units. Table 17.2 IrDA Registers Access Register Name Abbreviation Initial Value...
17.2 Register Description Specifications of the registers in the IrDA are the same as those in the SCIF except for the serial mode register described below. Therefore, refer to section 16, Serial Communication Interface with FIFO (SCIF), for details of these registers. 17.2.1 Serial Mode Register (SCSMR) Bit:...
Page 606
Bits 6 to 3—Ir Clock Select Bits (ICK3 to ICK0) Bit 2—Output Pulse Width Select (PSEL): PSEL selects an IrDA output pulse width that is 3/16 of the bit length for 115 kbps or 3/16 of the bit length for the selected baud rate. The Ir clock select bits should be set properly to fix the output pulse width at 3/16 of the bit length for 115 kbps by setting the PSEL bit to 1.
(SCSCR) is set to 1 (enabling transmission). When performing reception, clear the TE bit in SCSCR to 0. As the SH7709S's RxD1 pin is active-high in IrDA mode, a (Schmidt) inverter must be inserted when connecting an active-low IrDA module.
17.3.3 Receiving Received 3/16 IR frame bit-width pulses are demodulated and converted to a UART frame, as shown in figure 17.5. Demodulation to 0 is performed for pulse output, and demodulation to 1 is performed for no pulse output. UART frame Data Start bit Stop bit...
Section 18 Pin Function Controller 18.1 Overview The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the input/output direction. The pin function and input/output direction can be selected for each pin individually without regard to the operating mode of the chip. Table 18.1 lists the multiplexed pins.
18.2 Register Configuration Table 18.2 summarizes the registers of the pin function controller. Table 18.2 Pin Function Controller Registers Access Name Abbreviation Initial Value Address Size Port A control register PACR H'0000 H'04000100 (H'A4000100) * Port B control register PBCR H'0000 H'04000102 (H'A4000102) *...
18.3 Register Descriptions 18.3.1 Port A Control Register (PACR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port A control register (PACR) is a 16-bit readable/writable register that selects the pin functions.
18.3.2 Port B Control Register (PBCR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port B control register (PBCR) is a 16-bit readable/writable register that selects the pin functions.
18.3.3 Port C Control Register (PCCR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port C control register (PCCR) is a 16-bit readable/writable register that selects the pin functions.
18.3.4 Port D Control Register (PDCR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port D control register (PDCR) is a 16-bit readable/writable register that selects the pin functions.
18.3.5 Port E Control Register (PECR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port E control register (PECR) is a 16-bit readable/writable register that selects the pin functions.
18.3.6 Port F Control Register (PFCR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port F control register (PFCR) is a 16-bit readable/writable register that selects the pin functions.
18.3.7 Port G Control Register (PGCR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port G control register (PGCR) is a 16-bit readable/writable register that selects the pin functions.
Bit (2n + 1) Bit 2n PGnMD1 PGnMD0 Pin Function Other function (n = 1–3, 5) (see table 18.1) (Initial value) (ASEMD0 = 0) Reserved Port input (Pull-up MOS: on) (Initial value) (ASEMD0 = 1) Port input (Pull-up MOS: off) (n = 1 to 3, 5) Bit (2n + 1) Bit 2n...
Page 622
Bits 15 and 14—PH7 Mode 1, 0 (PH7MD1, PH7MD0): These bits select the pin functions and perform input pull-up MOS control. Bit 15 Bit 14 PH7MD1 PH7MD0 Pin Function Other function (see table 18.1) Port output Port input (Pull-up MOS: on) (Initial value) Port input (Pull-up MOS: off) Bits 13 and 12—PH6 Mode 1 and 0 (PH6MD1, PH6MD0)
18.3.9 Port J Control Register (PJCR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port J control register (PJCR) is a 16-bit readable/writable register that selects the pin functions.
18.3.10 Port K Control Register (PKCR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port K control register (PKCR) is a 16-bit readable/writable register that selects the pin functions.
18.3.11 Port L Control Register (PLCR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port L control register (PLCR) is a 16-bit readable/writable register that selects the pin functions.
18.3.12 SC Port Control Register (SCPCR) Bit: SCP7 SCP7 SCP6 SCP6 SCP5 SCP5 SCP4 SCP4 SCP3 SCP3 SCP2 SCP2 SCP1 SCP1 SCP0 SCP0 Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The SC port control register (SCPCR) is a 16-bit readable/writable register that selects the pin functions.
Page 627
Bits 11 and 10—SCP5 Mode 1 and 0 (SCP5MD1, SCP5MD0): These bits select the pin functions and perform input pull-up MOS control. Bit 11 Bit 10 SCP5MD1 SCP5MD0 Pin Function Other function (see table 18.1) Port output Port input (Pull-up MOS: on) (Initial value) Port input (Pull-up MOS: off) Bits 9 and 8—SCP4 Mode 1 and 0 (SCP4MD1, SCP4MD0): These bits select the pin function...
Page 628
Bits 5 and 4—SCP2 Mode 1 and 0 (SCP2MD1, SCP2MD0): These bits select the pin function and perform input pull-up MOS control. Bit 5 Bit 4 SCP2MD1 SCP2MD0 Pin Function Transmit data output 1 (TxD1) Receive data input 1 (RxD1) (Initial value) General output (SCPT[2] output pin) Receive data input 1 (RxD1)
Page 629
Bits 1 and 0—SCP0 Mode 1 and 0 (SCP0MD1, SCP0MD0): These bits select the pin function and perform input pull-up MOS control. Bit 1 Bit 0 SCP0MD1 SCP0MD0 Pin Function Transmit data output 0 (TxD0) Receive data input 0 (RxD0) (Initial value) General output (SCPT[0] output pin) Receive data input 0 (RxD0)
19.1 Overview The SH7709S has twelve 8-bit ports (ports A to L and SC). All port pins are multiplexed with other pin functions (the pin function controller (PFC) handles the selection of pin functions and pull-up MOS control). Each port has a data register which stores data for the pins.
19.2.2 Port A Data Register (PADR) Bit: PA7DT PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT Initial value: R/W: The port A data register (PADR) is an 8-bit readable/writable register that stores data for pins PTA7 to PTA0. Bits PA7DT to PA0DT correspond to pins PTA7 to PTA0. When the pin function is general output port, if the port is read the value of the corresponding PADR bit is returned directly.
19.3 Port B Port B is an 8-bit input/output port with the pin configuration shown in figure 19.2. Each pin has an input pull-up MOS, which is controlled by the port B control register (PBCR) in the PFC. PTB7 (input/output) / D31 (input/output) PTB6 (input/output) / D30 (input/output) PTB5 (input/output) / D29 (input/output) PTB4 (input/output) / D28 (input/output)
19.3.2 Port B Data Register (PBDR) Bit: PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT Initial value: R/W: The port B data register (PBDR) is an 8-bit readable/writable register that stores data for pins PTB7 to PTB0. Bits PB7DT to PB0DT correspond to pins PTB7 to PTB0. When the pin function is general output port, if the port is read the value of the corresponding PBDR bit is returned directly.
19.4 Port C Port C is an 8-bit input/output port with the pin configuration shown in figure 19.3. Each pin has an input pull-up MOS, which is controlled by the port C control register (PCCR) in the PFC. PTC7 (input/output) / PINT7 (input) / MSC7 (output) PTC6 (input/output) / PINT6 (input) / MSC6 (output) PTC5 (input/output) / PINT5 (input) / MSC5 (output) PTC4 (input/output) / PINT4 (input) / MSC4 (output)
19.4.2 Port C Data Register (PCDR) Bit: PC7DT PC6DT PC5DT PC4DT PC3DT PC2DT PC1DT PC0DT Initial value: R/W: The port C data register (PCDR) is an 8-bit readable/writable register that stores data for pins PTC7 to PTC0. Bits PC7DT to PC0DT correspond to pins PTC7 to PTC0. When the pin function is general output port, if the port is read, the value of the corresponding PCDR bit is returned directly.
19.5 Port D Port D comprises a 6-bit input/output port and 2-bit input port with the pin configuration shown in figure 19.4. Each pin has an input pull-up MOS, which is controlled by the port D control register (PDCR) in the PFC. PTD7 (input/output) / DACK1 (output) PTD6 (input) / DREQ1 (input) PTD5 (input/output) / DACK0 (output)
19.5.2 Port D Data Register (PDDR) Bit: PD7DT PD6DT PD5DT PD4DT PD3DT PD2DT PD1DT PD0DT Initial value: R/W: Note: * Undefined The port D data register (PDDR) is a 6-bit readable/writable and 2-bit read-only register that stores data for pins PTD7 to PTD0. Bits PD7DT to PD0DT correspond to pins PTD7 to PTD0. When the pin function is general output port, if the port is read, the value of the corresponding PDDR bit is returned directly.
19.6 Port E Port E is an 8-bit input/output port with the pin configuration shown in figure 19.5. Each pin has an input pull-up MOS, which is controlled by the port E control register (PECR) in the PFC. PTE7 (input/output) / AUDSYNC (output) PTE6 (input/output) PTE5 (input/output) / CE2B (output) PTE4 (input/output) / CE2A (output)
19.6.2 Port E Data Register (PEDR) Bit: PE7DT PE6DT PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT Initial value: R/W: The port E data register (PEDR) is an 8-bit readable/writable register that stores data for pins PTE7 to PTE0. Bits PE7DT to PE0DT correspond to pins PTE7 to PTE0. When the pin function is general output port, if the port is read the value of the corresponding PEDR bit is returned directly.
19.7 Port F Port F is an 8-bit input port with the pin configuration shown in figure 19.6. Each pin has an input pull-up MOS, which is controlled by the port F control register (PFCR) in the PFC. PTF7 (input) / PINT15 (input) / TRST (input) PTF6 (input) / PINT14 (input) / TMS (input) PTF5 (input) / PINT13 (input) / TDI (input) PTF4 (input) / PINT12 (input) / TCK (input)
19.7.2 Port F Data Register (PFDR) Bit: PF7DT PF6DT PF5DT PF4DT PF3DT PF2DT PF1DT PF0DT Initial value: R/W: Note: * Undefined The port F data register (PFDR) is an 8-bit read-only register that stores data for pins PTF7 to PTF0. Bits PF7DT to PF0DT correspond to pins PTF7 to PTF0. When the function is general input port, if the port is read the corresponding pin level is read.
19.8 Port G Port G comprises a 5-bit input/output port and 3-bit input port with the pin configuration shown in figure 19.7. Each pin has an input pull-up MOS, which is controlled by the port G control register (PGCR) in the PFC. PTG7 (input) / IOIS16 (input) PTG6 (input) / ASEMD0 (input) PTG5 (input) / ASEBRKAK (output)
19.8.2 Port G Data Register (PGDR) Bit: PG7DT PG6DT PG5DT PG4DT PG3DT PG2DT PG1DT PG0DT Initial value: R/W: Note: * Undefined The port G data register (PGDR) is an 8-bit read-only register that stores data for pins PTG7 to PTG0. Bits PG7DT to PG0DT correspond to pins PTG7 to PTG0. When the function is general input port, if the port is read the corresponding pin level is read.
19.9 Port H Port H comprises a 1-bit input/output port and 7-bit input port with the pin configuration shown in figure 19.8. Each pin has an input pull-up MOS, which is controlled by the port H control register (PHCR) in the PFC. PTH7 (input/output) / TCLK (output) PTH6 (input) / AUDCK (input) PTH5 (input) / ADTRG (input)
19.9.2 Port H Data Register (PHDR) Bit: PH7DT PH6DT PH5DT PH4DT PH3DT PH2DT PH1DT PH0DT Initial value: R/W: Note: * Undefined The port H data register (PHDR) is a 1-bit readable/writable and 7-bit read-only register that stores data for pins PTH7 to PTH0. Bits PH7DT to PH0DT correspond to pins PTH7 to PTH0. When the pin function is general output port, if the port is read, the value of the corresponding PHDR bit is returned directly.
19.10 Port J Port J is an 8-bit input/output port with the pin configuration shown in figure 19.9. Each pin has an input pull-up MOS, which is controlled by the port J control register (PJCR) in the PFC. PTJ7 (input/output) / STATUS1 (output) PTJ6 (input/output) / STATUS0 (output) PTJ5 (input/output) PTJ4 (input/output)
19.10.2 Port J Data Register (PJDR) Bit: PJ7DT PJ6DT PJ5DT PJ4DT PJ3DT PJ2DT PJ1DT PJ0DT Initial value: R/W: The port J data register (PJDR) is an 8-bit readable/writable register that stores data for pins PTJ7 to PTJ0. Bits PJ7DT to PJ0DT correspond to pins PTJ7 to PTJ0. When the pin function is general output port, if the port is read the value of the corresponding PJDR bit is returned directly.
19.11 Port K Port K is an 8-bit input/output port with the pin configuration shown in figure 19.10. Each pin has an input pull-up MOS, which is controlled by the port K control register (PKCR) in the PFC. PTK7 (input/output) / WE3 (output) / DQMUU (output) / ICIOWR (output) PTK6 (input/output) / WE2 (output) / DQMUL (output) / ICIORD (output) PTK5 (input/output) / CKE (output) PTK4 (input/output) / BS (output)
19.11.2 Port K Data Register (PKDR) Bit: PK7DT PK6DT PK5DT PK4DT PK3DT PK2DT PK1DT PK0DT Initial value: R/W: The port K data register (PKDR) is an 8-bit readable/writable register that stores data for pins PTK7 to PTK0. Bits PK7DT to PK0DT correspond to pins PTK7 to PTK0. When the pin function is general output port, if the port is read, the value of the corresponding PKDR bit is returned directly.
19.12 Port L Port L is an 8-bit input port with the pin configuration shown in figure 19.11. PTL7 (input) / AN7 (input) / DA0 (input) PTL6 (input) / AN6 (input) / DA1 (input) PTL5 (input) / AN5 (input) PTL4 (input) / AN4 (input) Port L PTL3 (input) / AN3 (input) PTL2 (input) / AN2 (input)
19.12.2 Port L Data Register (PLDR) Bit: PL7DT PL6DT PL5DT PL4DT PL3DT PL2DT PL1DT PL0DT Initial value: R/W: The port L data register (PLDR) is an 8-bit read-only register that stores data for pins PTL7 to PTL0. Bits PL7DT to PL0DT correspond to pins PTL7 to PTL0. When the function is general input port, if the port is read, the corresponding pin level is read.
19.13 SC Port The SC port comprises a 4-bit input/output port, 3-bit output port, and 4-bit input port with the pin configuration shown in figure 19.12. Each pin has an input pull-up MOS, which is controlled by the SC port control register (SCPCR) in the PFC. SCPT7 (input) / CTS2 (input) / IRQ5 (input) SCPT6 (input/output) / RTS2 (output) SCPT5 (input/output) / SCK2 (input/output)
19.13.2 SC Port Data Register (SCPDR) Bit: SCP7DT SCP6DT SCP5DT SCP4DT SCP3DT SCP2DT SCP1DT SCP0DT Initial value: R/W: Note: * Undefined The SC port data register (SCPDR) is a 7-bit readable/writable and 1-bit read-only register that stores data for pins SCPT7 to SCPT0. Bits SCP7DT to SCP0DT correspond to pins SCPT7 to SCPT0.
Table 19.24 Read/Write Operation of the SC Port Data Register (SCPDR) SCPnMD1 SCPnMD0 Pin State Read Write Other function SCPDR value Value is written to SCPDR, but does (see table 18.1) not affect pin state Output SCPDR value Write value is output from pin Input (Pull-up Pin state Value is written to SCPDR, but does...
Section 20 A/D Converter 20.1 Overview The SH7709S includes a 10-bit successive-approximation A/D converter allowing selection of up to eight analog input channels. 20.1.1 Features A/D converter features are listed below. 10-bit resolution Eight input channels High-speed conversion Conversion time: maximum 15 s per channel (P = 33 MHz operation)
20.1.2 Block Diagram Figure 20.1 shows a block diagram of the A/D converter. Internal Peripheral data bus data bus 10-bit Analog Control circuit multi- Comparator plexer Sample-and- hold circuit interrupt signal ADTRG A/D converter Legend ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C...
20.1.3 Input Pins Table 20.1 summarizes the A/D converter’s input pins. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AV and AV are the power supply inputs for the analog circuits in the A/D converter. AVcc also functions as the A/D converter reference voltage pin.
20.2 Register Descriptions 20.2.1 A/D Data Registers A to D (ADDRA to ADDRD) Upper register: H Bit: Initial value: R/W: Lower register: L Bit: — — — — — — Initial value: R/W: n = A to D The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion.
20.2.2 A/D Control/Status Register (ADCSR) Bit: ADIE ADST MULTI Initial value: R/(W) * R/W: Note: * Write 0 to clear the flag. ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H'00 by a reset and in standby mode. Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Page 663
Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin. Bit 5: ADST Description A/D conversion is stopped (Initial value) (1) Single mode: A/D conversion starts;...
Page 664
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the MULTI bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Channel Selection Description Single Mode Multi Mode and Scan (MULTI = 0) Mode (MULTI = 1) AN0 (Initial value)
20.2.3 A/D Control Register (ADCR) Bit: TRGE1 TRGE0 RESVD1 RESVD2 — — — Initial value: R/W: ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion. ADCR is initialized to H'07 by a reset and in standby mode. Bit 7 and 6—Trigger Enable (TRGE1, TRGE0): Enables or disables external triggering of A/D conversion.
20.3 Bus Master Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the bus master by the upper 8 bits of the 16-bit peripheral data bus. Therefore, although the upper byte can be accessed directly by the bus master, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows.
20.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has three operating modes: single mode, multi mode, and scan mode. 20.4.1 Single Mode (MULTI = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input.
20.4.2 Multi Mode (MULTI = 1, SCN = 0) Multi mode should be selected when performing A/D conversions on one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1).
20.4.3 Scan Mode (MULTI = 1, SCN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1)).
20.4.4 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 20.6 shows the A/D conversion timing.
Table 20.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol A/D conversion start — — delay Input sampling time — — — — A/D conversion time — — CONV Note: Values in the table are numbers of states (t 20.4.5 External Trigger Input Timing A/D conversion can be externally triggered.
20.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 20.6 Definitions of A/D Conversion Accuracy The A/D converter compares an analog value input from an analog input channel with its analog reference value and converts it to 10-bit digital data.
The case is shown here in which H'3FF is obtained when AV is input as an analog input. FF is the data containing the upper 8 bits of the conversion result, and C0 is the data containing the lower 2 bits. SH7709S AN0 to AN7 0.1 F Note: 10 F 0.01 F...
Table 20.5 Analog Input Pin Ratings Item Unit Analog input capacitance — Allowable signal-source impedance — Table 20.6 Relationship between Access Size and Read Data Bus Width 32 Bits (D31–D0) 16 Bits (D15–D0) 8 Bits (D7–D0) Endian Access Size Command Little Little Little...
Section 21 D/A Converter 21.1 Overview The SH7709S includes a D/A converter with two channels. 21.1.1 Features D/A converter features are listed below. Eight-bit resolution Two output channels Conversion time: maximum 10 s (with 20-pF capacitive load) Output voltage: 0 V to AVcc 21.1.2...
21.1.3 I/O Pins Table 21.1 summarizes the D/A converter’s input and output pins. Table 21.1 D/A Converter Pins Pin Name Abbreviation Function Analog power supply pin AVcc Input Analog power supply Analog ground pin AVss Input Analog ground and reference voltage Analog output pin 0 Output Analog output, channel 0...
21.2 Register Descriptions 21.2.1 D/A Data Registers 0 and 1 (DADR0/1) Bit: Initial value: R/W: The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the data to be converted. When analog output is enabled, the D/A data register values are constantly converted and output at the analog output pins.
Page 682
Bit 5—D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1. When the DAE bit is cleared to 0, D/A conversion is controlled independently in channels 0 and 1. When the chip enters standby mode while D/A conversion is enabled, the D/A output is held and the analog power-supply current is equivalent to that during D/A conversion.
21.3 Operation The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1.
Group, IEEE Standard 1149.1 and IEEE Standard Test Access Port and Boundary-Scan Architecture) specifications. The UDI in the SH7709S supports a boundary scan mode, and is also used for emulator connection. When using an emulator, UDI functions should not be used. Refer to the emulator manual for the method of connecting the emulator.
mode, boundary scan and emulator functions can be used. The input level at the ASEMD0 pin should be held for at least one cycle after RESETP negation. A A A A S S S S E E E E B B B B R R R R KAK KAK: Dedicated emulator pin 22.2.2 Block Diagram...
Boundary Scan Register (SDBSR) The boundary scan register (SDBSR) is a shift register, located on the PAD, for controlling the input/output pins of the SH7709S. Using the EXTEST and SAMPLE/PRELOAD commands, a boundary scan test conforming to the JTAG standard can be carried out. Table 22.3 shows the correspondence between the pins of this LSI and boundary scan register bits.
Table 22.3 Pins of this LSI and Boundary Scan Register Bits Pin Name Pin Name from TDI D31/PTB7 D30/PTB6 D29/PTB5 D28/PTB4 D27/PTB3 IRQ0/IRL0/PTH0 D26/PTB2 IRQ1/IRL1/PTH1 D25/PTB1 IRQ2/IRL2/PTH2 D24/PTB0 IRQ3/IRL3/PTH3 D23/PTA7 IRQ4/PTH4 D22/PTA6 D31/PTB7 D21/PTA5 D30/PTB6 D20/PTA4 D29/PTB5 D19/PTA3 D28/PTB4 D18/PTA2 D27/PTB3 D17/PTA1 D26/PTB2...
Page 690
Pin Name Pin Name Control Control Control Control Control Control Control Control Control Control Control D31/PTB7 Control Control D30/PTB6 Control Control BS/PTK4 D29/PTB5 Control WE2/DQMUL/ICIORD/ D28/PTB4 Control PTK6 WE3/DQMUU/ICIORD/ D27/PTB3 Control PTK7 AUDSYNC/PTE7 D26/PTB2 Control CS2/PTK0 D25/PTB1 Control CS3/PTK1 D24/PTB0 Control CS4/PTK2 D23/PTA7...
Page 691
Pin Name Pin Name CS4/PTK2 CS5/CE1A/PTK3 CS6/CE1B CE2A/PTE4 CE2B/PTE5 Control Control Control Control Control Control Control Control Control Control Control Control Control Control BS/PTK4 Control Control WE0/DQMLL Control WE1/DQMLU/WE Control WE2/DQMUL/ICIORD/ Control PTK6 WE3/DQMUU/ICIOWR/ Control PTK7 RD/WR Control AUDSYNC/PTE7 Control CS0/MCS0 Control CS2/PTK0...
Page 692
Pin Name Pin Name BREQ Control WAIT BS/PTK4 Control Control AUDCK/PTH6 WE0/DQMLL IOIS16/PTG7 Control WE1/DQMLU/WE ASEBRKAK/PTG5 Control WE2/DQMUL/ICIORD/ Control CKIO2/PTG4 PTK6 WE3/DQMUU/ICIOWR/ Control AUDATA3/PTG3 PTK7 RD/WR Control AUDATA2/PTG2 AUDSYNC/PTE7 Control AUDATA1/PTG1 CS0/MCS0 Control AUDATA0/PTG0 CS2/PTK0 ADTRG/PTH5 Control CS3/PTK1 IRLS3/PTF3/PINT11 Control CS4/PTK2 IRLS2/PTF2/PINT10 Control...
Page 693
Pin Name Pin Name ASEBRKAK/PTG5 RxD2/SCPT4 WAKEUP/PTD3 AUDATA3/PTG3 RESETOUT/PTD2 AUDATA2/PTG2 AUDATA1/PTG1 DRAK0/PTD1 AUDATA0/PTG0 DRAK1/PTD0 DREQ0/PTD4 CKE/PTK5 Control RAS3L/PTJ0 DREQ1/PTD6 Control PTJ1 Control RxD1/SCPT2 CASL/PTJ2 CTS2/IRQ5/SCPT7 Control CASU/PTJ3 MCS7/PTC7/PINT7 Control MCS6/PTC6/PINT6 PTJ4 Control MCS5/PTC5/PINT5 PTJ5 Control MCS4/PTC4/PINT4 DACK0/PTD5 Control MCS3/PTC3/PINT3 DACK1/PTD7 Control MCS2/PTC2/PINT2 PTE6...
Page 694
Pin Name Pin Name MCS6/PTC6/PINT6 SCK1/SCPT3 Control MCS5/PTC5/PINT5 TxD2/SCPT4 Control MCS4/PTC4/PINT4 SCK2/SCPT5 Control WAKEUP/PTD3 RTS2/SCPT6 Control RESETOUT/PTD2 MCS7/PTC7/PINT7 Control MCS3/PTC3/PINT3 MCS6/PTC6/PINT6 Control MCS2/PTC2/PINT2 MCS5/PTC5/PINT5 Control MCS1/PTC1/PINT1 MCS4/PTC4/PINT4 Control MCS0/PTC0/PINT0 WAKEUP/PTD3 Control RESETOUT/PTD2 DRAK0/PTD1 Control MCS3/PTC3/PINT3 DRAK1/PTD0 Control MCS2/PTC2/PINT2 STATUS0/PTJ6 Control Control MCS1/PTC1/PINT1 STATUS1/PTJ7...
22.4 UDI Operation 22.4.1 TAP Controller Figure 22.2 shows the internal states of the TAP controller. State transitions basically conform with the JTAG standard. Test-logic-reset Run-test/idle Select-DR-scan Select-IR-scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR Figure 22.2 TAP Controller State Transitions Note: The transition condition is the TMS value at the rising edge of TCK.
22.4.2 Reset Configuration Table 22.4 Reset Configuration ASEM M M M D D D D 0 0 0 0 * R R R R ESE ESET T T T P P P P T T T T R R R R S S S S T T T T Chip State High-level Low-level...
22.4.3 UDI Reset An UDI reset is executed by setting an UDI reset assert command in SDIR. An UDI reset is of the same kind as a power-on reset. An UDI reset is released by inputting an UDI reset negate command.
22.5 Boundary Scan A command can be set in SDIR by the UDI to place the UDI pins in the boundary scan mode stipulated by JTAG. 22.5.1 Supported Instructions This LSI supports the three essential instructions defined in the JTAG standard (BYPASS, SAMPLE/PRELOAD, and EXTEST).
Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). The instruction code is 0000. 22.5.2 Points for Attention 1. Boundary scan mode covers clock-related signals (EXTAL, EXTAL2, XTAL, XTAL2, CKIO).
Section 23 Electrical Characteristics 23.1 Absolute Maximum Ratings Table 23.1 shows the absolute maximum ratings. Table 23.1 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage (I/O) VccQ –0.3 to 4.2 Power supply voltage (internal) Vcc –0.3 to 2.5 Vcc –...
Page 702
(Max. 1 ms) 3.3 V 3.3 V power 1.7 V/1.8 V/1.9 V/2.0 V 1.7 V/1.8 V/1.9 V/2.0 V power RESETP Pin states undefined All other pins* Pin states undefined Power-on reset state Note: * Except power/GND, clock related, and analog pins Power-On Sequence Power-off order 1.
23.2 DC Characteristics Tables 23.2 and 23.3 list DC characteristics. Table 23.2 DC Characteristics Ta = –20 to 75°C Item Symbol Unit Measurement Conditions Power supply voltage VccQ 200 MHz model * Vcc, 1.85 2.00 2.15 Vcc-PLL1, 1.75 1.90 2.05 167 MHz model Vcc-PLL2, 1.65...
Page 704
Item Symbol Unit Measurement Conditions RESETP, Input high VccQ — VccQ + RESETM, voltage NMI, IRQ5 to IRQ0, MD5 to MD0, IRL3 to IRL0, IRLS3 to IRLS0, PINT15 to PINT0, ASEMD0, ADTRG, TRST, EXTAL, CKIO, RxD1, EXTAL2 — — — When not connecting to a crystal oscillator, connect to Vcc.
Page 705
Item Symbol Min Unit Measurement Conditions RESETP, Input low –0.3 — VccQ RESETM, voltage NMI, IRQ5–IRQ0, MD5–MD0, IRL3 to IRL0, IRLS3 to IRLS0, PINT15– PINT0, ASEMD0, ADTRG, TRST, EXTAL, CKIO, RxD1, EXTAL2 — — — When not connecting to a crystal oscillator, connect to Vcc.
Item Symbol Min Unit Measurement Conditions Analog AVcc power- supply voltage Analog During A/D AIcc — power- conversion supply current During A/D — and D/A conversion Idle — µA Ta = 25°C Notes: Even when PLL is not used, always connect Vcc-PLL1 and Vcc-PLL2 to Vcc and connect Vss-PLL1 and Vss-PLL2 to Vss.
23.3 AC Characteristics In general, inputting for this LSI should be clock synchronous. Keep the setup and hold times for each input signal unless otherwise specified. Table 23.4 Operating Frequency Range VccQ = 3.3 ± 0.3 V, VccQ = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C Item Symbol Unit...
Stable oscillation CKIO, internal clock RESPW RESPS OSC1 RESETP Note: Oscillation settling time when built-in oscillator is used Figure 23.4 Power-on Oscillation Settling Time Stable oscillation Standby CKIO, internal clock RESPW/MW RESPS/MS OSC2 RESETP RESETM Note: Oscillation settling time when built-in oscillator is used in the oscillation off mode Figure 23.5 Oscillation Settling Time at Standby Return (Return by Reset) Rev.
Standby Stable oscillation CKIO, internal clock OSC3 WAKEUP Note: Oscillation settling time when built-in oscillator is used in the oscillation off mode Figure 23.6 Oscillation Settling Time at Standby Return (Return by NMI) Standby Stable oscillation CKIO, internal clock OSC4 IRL3 to IRL0 IRQ4 to IRQ0 PINT0/1...
Reset or NMI interrupt request Stable input clock Stable input clock EXTAL input or CKIO input PLL synchronization PLL synchronization PLL1 PLL output, CKIO output Internal clock STATUS 0 Normal Standby Normal STATUS 1 Note: PLL oscillation settling time during the continued oscillation mode or when clock is input from EXTAL pin or CKIO pin Figure 23.8 PLL Synchronization Settling Time during Standby Recovery (Reset or NMI) IRQ4 –...
23.3.2 Control Signal Timing Table 23.6 Control Signal Timing Vcc = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C Item Symbol Unit Figure RESETP pulse width 20 * —...
CKIO RESPS/MS RESPS/MS RESPW/MW RESETP RESETM Figure 23.11 Reset Input Timing CKIO RESPH/MH RESPS/MS RESETP RESETM NMIH NMIS IRQH IRQS IRQ5 to IRQ0 Figure 23.12 Interrupt Signal Input Timing CKIO IRQOD IRQOD IRQOUT Figure 23.13 I I I I R R R R QOU QOUT T T T Timing Rev.
CKIO BREQH BREQS BREQH BREQS BREQ BACKD BACKD BACK BON2 BOFF2 RD, RD/WR , RAS, CAS , CSn, WEn, BS, BON1 MCSn BOFF1 A25 to A0, D31 to D0 Figure 23.14 Bus Release Timing Normal mode Standby mode Normal mode CKIO STATUS 0 STATUS 1...
23.3.3 AC Bus Timing Table 23.7 Bus Timing Clock Modes 0/1/2/7, VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C Item Symbol Max Unit Figure Address delay time 23.16–23.36, 23.39–23.46 Address setup time —...
Page 718
Item Symbol Max Unit Figure ICIORD delay time — 23.44–23.46 ICRSD ICIOWR delay time — 23.44–23.46 ICWSD IOIS16 setup time — 23.45, 23.46 IO16S IOIS16 hold time — 23.45, 23.46 IO16H DACK delay time 1 — 23.16–23.36, 23.39–23.46 DAKD1 (Reference for CKIO rise) DACK delay time 2 —...
23.3.5 Burst ROM Timing CKIO A25 to A4 A3 to A0 CSD1 CSD2 RDH1 RD/WR RDH1 RDH1 RDS1 D31 to D0 DAKD1 DAKD2 DACKn WAIT Note: In the write cycle, the basic bus cycle, the basic bus cycle is performed. Figure 23.19 Burst ROM Bus Cycle (No Wait) Rev.
CKIO A25 to A4 A3 to A0 CSD2 CSD1 RDH1 RD/WE RDH1 RDH1 RDH1 RDS1 RDS1 D31 to D0 DAKD1 DAKD2 DACKn WAIT Note: In the write cycle, the basic bus cycle is performed. Figure 23.20 Burst ROM Bus Cycle (Two Waits) Rev.
CKIO A25 to A4 A3 to A0 CSD2 CSD1 RDH1 RD/WR RSD1 RSD1 RDH1 RDH1 RDS1 D31 to D0 DAKD2 DAKD1 DACKn WAIT Note: In the write cycle, the basic bus cycle is performed. Figure 23.21 Burst ROM Bus Cycle (External Wait, WAITSEL = 1) Rev.
pcm1 pcm2 pcm1 pcm2 pcm1 pcm2 pcm1 pcm2 CKIO A25 to A4 A3 to A0 CSD1 CSD1 CExx RD/WR (read) RDH1 RDH1 RDS1 RDS1 D15 to D0 (read) DAKD1 DAKD1 DACKn Note: Even though burst mode is set, write cycle operation is the same as in normal mode. Figure 23.42 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait) Rev.
pcm0 pcm1 pcm1w pcm1w pcm1w pcm2 pcm1 pcm1w pcm2 pcm2w CKIO A25 to A4 A3 to A0 CSD1 CSD1 CExx RD/WR (read) RDH1 RDH1 RDS1 RDS1 D15 to D0 (read) DAKD1 DAKD1 DACKn WAIT Note: Even though burst mode is set, the write cycle operation is the same as in normal mode. Figure 23.43 PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, Two Waits, Burst Pitch = 3, WAITSEL = 1) Rev.
RESETP TRSTS TRSTH TRST Figure 23.56 T T T T R R R R S S S S T T T T Input Timing (Reset Hold) TCKCYC TDIS TDIH TMSS TMSH TDOD Figure 23.57 UDI Data Transfer Timing RESETP ASEMD0S ASEMD0H ASEMD0 Figure 23.58 A A A A S S S S E E E E M M M M D D D D 0 0 0 0 Input Timing...
23.3.10 AC Characteristics Measurement Conditions I/O signal reference level: VccQ/2 (VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V) Input pulse level: Vss to 3.0 V (where RESETP, RESETM, ASEND0, IRLS3 to IRLS0, IRL3 to IRL0, ADTRG, PINT15 to PINT0, TRST, RxD1, CA, NMI, IRQ5–IRQ0, CKIO, and MD5–MD0 are within Vss to Vcc) Input rise and fall times: 1 ns DUT output...
23.3.11 Delay Time Variation Due to Load Capacitance A graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 or 50 pF) is connected to this LSI's pins is shown below. The graph shown in figure 23.60 should be taken into consideration in the design process if the stipulated capacitance is exceeded in connecting an external device.
Appendix A Pin Functions Pin States Table A.1 shows pin states during resets, power-down states, and the bus-released state. Table A.1 Pin States during Resets, Power-Down States, and Bus-Released State Reset Power-Down Category Power-On Manual Released Standby Sleep Reset Reset Clock EXTAL XTAL...
Page 760
Reset Power-Down Category Power-On Manual Released Standby Sleep Reset Reset ZL * Address bus A[25:0] Data bus D[15:0] IP * ZK * IOP * ZP * D[23:16]/PTA[7:0] IP * ZK * IOP * ZP * D[31:24]/PTB[7:0] CS0/MCS0 ZH * Bus control CS[2:4]/PTK[0:2] OP * ZH *...
Page 761
Reset Power-Down Category Power-On Manual Released Standby Sleep Reset Reset ZI * IZ * IZ * SCI/Smart card RxD0/SCPT[0] without FIFO ZO * ZK * OZ * OZ * TxD0/SCPT[0] ZP * ZK * IOP * IOP * SCK0/SCPT[1] ZI * IZ * IZ * SCIF/IrDA...
Page 762
Reset Power-Down Category Power-On Manual Released Standby Sleep Reset Reset ZI * Analog AN[5:0]/PTL[5:0] ZI * OZ * IO * IO * AN[6:7]/DA[1:0]/PTL[6:7] Input O: Output H: High-level output L: Low-level output Z: High impedance P: Input or output depending on register setting K: Input pin is high impedance, output pin holds its state V: I/O buffer off, pull-up MOS on Notes: 1.
Page 764
Pin No. Pin No. (FP-208C, Function (BP-240A) FP-208E) A25 to A0 86, 84, 82, 80, V12, T12, Address bus 78 to 72, 70, V11, W10, 68 to 60, 58, V10, U9, T9, 56 to 53 V9, W9, T8, U8, W8, U7, V7, W7, T6, U6, V6, W6, T5, U5, W5,...
Page 765
Pin No. Pin No. (FP-208C, Function (BP-240A) FP-208E) CS2/PTK[0] Chip select 2 / I/O port CS0/MCS0 Chip select 0 / Mask ROM chip select 0 BS/PTK[4] Bus cycle start / I/O port PTJ[5] I/O port PTJ[4] I/O port CASU/PTJ[3] CAS(SDRAM) / I/O port CASL/PTJ[2] CAS(SDRAM) / I/O port DACK0/PTD[5]...
Page 766
Pin No. Pin No. (FP-208C, Function (BP-240A) FP-208E) CKIO2/PTG[4] System clock output / input port AUDATA[3]/ AUD data / input port PTG[3] AUDATA[2]/ AUD data / input port PTG[2] AUDATA[1]/ AUD data / input port PTG[1] AUDATA[0]/ AUD data / input port PTG[0] TRST/PTF[7]/ Test reset / input port / port interrupt...
Page 767
Pin No. Pin No. (FP-208C, Function (BP-240A) FP-208E) CKIO System clock I/O XTAL2 Crystal oscillator pin (for on-chip RTC) EXTAL2 Crystal oscillator pin (for on-chip RTC) CKE/PTK[5] CK enable for SDRAM / I/O port Setting hardware standby pin 21, 35, 47, 59, H4, M1, R1, Power Power supply (3.3 V)
Treatment of Unused Pins When RTC is not used EXTAL2: Pull up (2.0/1.9/1.8/1.7 V) XTAL2: Leave unconnected –RTC: Power supply (2.0/1.9/1.8/1.7 V) –RTC: Power supply (0 V) When PLL2 is not used CAP2: Leave unconnected –PLL2: Power supply (2.0/1.9/1.8/1.7 V) –PLL2: Power supply (0 V) When on-chip crystal oscillator is not used XTAL:...
Pin States in Access to Each Address Space Table A.3 Pin States (Ordinary Memory/Little Endian) 8-Bit Bus Width 16-Bit Bus Width Byte/Word/Long- Byte Access Byte Access Word/Longword word Access (Address 2n) (Address 2n + 1) Access CS6 to CS2, CS0 Enabled Enabled Enabled...
Table A.4 Pin States (Ordinary Memory/Big Endian) 8-Bit Bus Width 16-Bit Bus Width Byte/Word/Long- Byte Access Byte Access Word/Longword word Access (Address 2n) (Address 2n + 1) Access CS6 to CS2, CS0 Enabled Enabled Enabled Enabled R Low W High High High High...
Register Bits Table B.2 Register Bits Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SDMR — — — — SCSMR STOP CKS1 CKS0 SCBRR SCSCR MPIE TEIE CKE1 CKE0 SCTDR SCSSR TDRE RDRF...
Page 790
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR1 — — — — — — — — — UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TCOR2 TCNT2 TCR2 — — — —...
Page 791
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module RCR1 — — — — RCR2 PES2 PES1 PES0 RTCEN RESET START ICR0 — — — — — — NMIE INTC — —...
Page 792
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module RFCR — — — — — — — — FRQCR STC2 IFC2 PFC2 — — — CKOEN SLPFRQ PLLEN PSTBY STC1 STC0 IFC1 IFC0 PFC1...
Page 793
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BAMRA BBRA — — — — — — — — CDA1 CDA0 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0 BETR — — — —...
Page 794
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BASRA BASRB — — — — — — — — — — — — — — — — — — — — —...
Page 795
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module IRR0 INTC PINT0R PINT1R IRQ5R IRQ4R IRQ3R IRQ2R IRQ1R IRQ0R IRR1 INTC TXI1R BRI1R RXI1R ERI1R DEI3R DEI2R DEI1R DEI0R IRR2 INTC —...
Page 796
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module CHCR0 — — — — — — — — DMAC — — — — — — SAR1 DMAC DAR1 DMAC DMATCR1 — —...
Page 797
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module CHCR2 — — — — — — — — DMAC — — — — — — — — — SAR3 DMAC DAR3 DMAC DMATCR3 —...
Page 798
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ADDRBH A/DC ADDRBL — — — — — — A/DC ADDRCH A/DC ADDRCL — — — — — — A/DC ADDRDH A/DC ADDRDL —...
Page 799
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PGCR PG7M PG7M PG6M PG6M PG5M PG5M PG4M PG4M PORT PG3M PG3M PG2M PG2M PG1M PG1M PG0M PG0M PHCR PH7M PH7M PH6M PH6M PH5M PH5M...
Appendix C Product Lineup Table C.1 SH7709S Models Power Supply Voltage Operating Abbr. Model Marking Package Frequency Internal SH7709S 3.3±0.3 V 2.0±0.15 V 200 MHz HD6417709SHF200B 208-pin plastic HQFP (FP-208E) 1.9±0.15 V 167 MHz HD6417709SF167B 208-pin plastic LQFP (FP-208C) HD6417709SBP167B...
Page 806
Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd.
Page 807
SH7709S Group Hardware Manual REJ09B0081-0500O (ADE-602-250C)
Need help?
Do you have a question about the SH7709S and is the answer not in the manual?
Questions and answers