Bit Pattern Interpolation - ICP DAS USA I-8092F User Manual

A.4.3 Bit Pattern Interpolation
This interpolation driving receives interpolation data that is created by upper-level CPU and
transformed to bit patterns in a block of a predetermined size, and outputs interpolation pulses
consecutively at the specified drive speed. Every axis has 2 bit-data buffers for host CPU: one for
+ direction and the other for - direction. When performing the bit pattern interpolation, the host
CPU will write the designated interpolation data, for 2 or 3 axes, into I-8092F. If a bit in the bit
pattern data from CPU is "1", I-8092F will output a pulse at the time unit; if it is "0", I-8092F will not
output any pulse at the time unit. For example, if the user want to generate the X-Y profile (see
Fig. A-27), the host CPU must write a set of pattern into those specific registers ---- XPP: the +
direction register for X axis, XPM: the − direction register for X axis, YPP and YPM: the + and −
directions registers. With in the time unit, I-8092F will check the registers once and decide to
output a pulse or not depending on the bit pattern.
Stacking counter (SC) is a 2-bit counter. Its value is between 0 and 3, which can be read
from D14, 13 of register RR0. SC will decide which register for the data from the host CPU. The
initial value of SC is 0. So, when host CPU writes bit pattern data into BP1P or BP1M, the data
will be stored in SREG, and then, SC will count up to 1, and the next data from the host CPU will
be written into REG1. By this way, the REG2 becomes the register when SC=2. The host CPU is
not able to write any bit pattern data into MCX312 when SC=3.
When the bit pattern interpolation pulse is outputting, D0 in SREG (Stack Register) will be
shifted output first, and then in the order of D1, D....When all of SREGs (Stack Registers) have
been shifted output, the data in REG1 will be shifted to SREG, the data in REG2 will be shifted to
REG1, and the SC will count down to 2. Then, the host CPU is able to write a new data into
MCX312 again.
In order to make MCX312 output the bit pattern data continuously, the host CPU should
write the data into MCX312 before SC counts down to 0. MCX312 will output an interrupt
requirement signal to host CPU when SC counts down from 2 to 1.
ICPDAS
Fig. A-26 Bit pattern data for X-Y profile
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I-8092F Software User Manual