Expansion Connectors - ARM MPS2 Technical Reference Manual

5.2

Expansion connectors

The MPS2 and MPS2+ FPGA Prototyping Boards each provide two IDC header connectors that support
user expansion.
The following figure shows the IDC expansion connector.
The following two tables show the pin mappings for the IDC expansion connectors EXP1, component
number J7, and EXP2, component number J8, which support general‑purpose I/O expansion.
Pins 9, 13, 14, and 25 of connector EXP1 have source series terminating resistors. These resistors help to
maintain the integrity of high slew-rate signals. Arm recommends these pins for use as clock outputs or
sensitive data outputs in preference to other pins.
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2
1
Figure 5-6 IDC expansion connector
Table 5-6 Expansion connector EXP1, J7, signal list
Pin Signal
1 EXP0
3 EXP1
5 EXP2
7 EXP3
9 EXP4 SI Clock output
11 GND
13 EXP5 SI Clock output
15 EXP6
17 EXP7
19 EXP8
21 EXP9
23 EXP10
25 EXP11 SI Clock output 26
27 3V
29 GND
31 EXP12
33 EXP13
Table 5-7 Expansion connector EXP2, J8, signal list
Pin Signal
1 EXP26
3 EXP27
5 EXP28
5 Signal Descriptions
5.2 Expansion connectors
34
33
Pin Signal
2 EXP14
4 EXP15
6 EXP16
8 EXP17
10 EXP18
12 GND
14 EXP19 Clock output
16 EXP20
18 EXP21
20 EXP22
22 EXP23
24 GND
3V
28 GND
30 3V
32 EXP24
34 EXP25
Pin Signal
2 EXP40
4 EXP41
6 EXP42
5-80