Overview Of The Mps2 And Mps2+ Hardware - ARM MPS2 Technical Reference Manual

2.1

Overview of the MPS2 and MPS2+ hardware

The hardware infrastructure supports Arm M-class processor evaluation and development, system
expansion, and debug interfaces.
The following figure shows the high-level hardware infrastructure.
The image that the configuration systems loads into the FPGA at powerup defines the functionality of the
MPS2 and MPS2+ FPGA Prototyping Boards.
MPS2/MPS2+ FPGA Prototyping Board
Configuration
EEPROM
3V
battery
Real Time Clock
USB 2.0
LEDs
DIP switches
ON/OFF/Soft RESET
push button
Hardware RESET push
button
JTAG 20 P-JTAG/SWD
CoreSight 10
P-JTAG/SWD
P-JTAG/SWD
CoreSight 20
4-bit Trace
P-JTAG/SWD
MICTOR 38
16-bit Trace
100112_0200_09_en
Note
microSD card
(USBMSD)
Configuration
MCC
CMSIS-DAP
P-JTAG/SWD
4-bit Trace
16-bit Trace
Copyright © 2013–2016, 2018–2020 Arm Limited or its affiliates. All
2.1 Overview of the MPS2 and MPS2+ hardware
UART ETHERNET
MAC/PHY
SCC
Clock
generators
FPGA
2
I S
2
I C
audio
Stereo audio
codec
Audio Audio
Figure 2-1 Board hardware infrastructure
rights reserved.
Non-Confidential
2 Hardware Description
PSRAM 0
8MB
PSRAM 1
16-bit
8MB
ZBT SSRAM 1
64-bit 32-bit
2MB
ZBT SSRAM 1
32-bit
2MB
ZBT SSRAM 2
32-bit
2MB
ZBT SSRAM 3
32-bit
2MB
SPI SPI
EXP[25:0] Expansion
EXP[51:26] Expansion
CLCD CLCD
VGA VGA
F-JTAG JTAG 14
LEDs
User push buttons
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