Part 2.5: Ddr3 Dram - Alinx ARTIX-7FPGA User Manual

Part 2.5: DDR3 DRAM

The FPGA core board AC7200 is equipped with two Micron 4Gbit (512MB)
DDR3 chips,
MT41K256M16HA-125). The DDR3 SDRAM has a maximum operating speed
of 800MHz (data rate 1600Mbps). The DDR3 memory system is directly
connected to the memory interface of the BANK 34 and BANK35 of the FPGA.
The specific configuration of DDR3 SDRAM is shown in Table 4-1.
Bit Number
U5,U6
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.
www.alinx.com
ARTIX-7 FPGA Development Board AX7203 User Manual
model MT41J256M16HA-125
Chip Model
MT41J256M16HA-125
DDR3 SDRAM Configuration
The DDR3 DRAM Schematic
(compatible
Capacity Factory
256M x 16bit
with
Micron
15 /