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PIN73
B15_L24_N
PIN75
NC
PIN77
FPGA_TCK
PIN79
FPGA_TDO
Board to Board Connectors CON4
The 80-Pin connector CON4 is used to extend the normal IO and GTP
high-speed data and clock signals of the FPGA BANK16. The voltage standard
of the IO port of BANK16 can be adjusted by an LDO chip. The default installed
LDO is 3.3V. If the user wants to output other standard levels, it can be
replaced by a suitable LDO. The high-speed data and clock signals of the GTP
are strictly differential routed on the core board. The data lines are equal in
length and kept at a certain interval to prevent signal interference.
Pin Assignment of Board to Board Connectors CON4
CON1
Signal Name
Pin
PIN1
NC
PIN3
NC
PIN5
NC
PIN7
NC
PIN9
GND
PIN11
NC
PIN13
NC
PIN15
GND
PIN17
MGT_TX3_P
PIN19
MGT_TX3_N
PIN21
GND
PIN23
MGT_RX3_P
PIN25
MGT_RX3_N
PIN27
GND
PIN29
MGT_TX1_P
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ARTIX-7 FPGA Development Board AX7203 User Manual
M16
3.3V
-
V12
3.3V
U13
3.3V
FPGA Pin Voltage
Level
-
-
-
-
-
Ground
-
-
-
Ground
D7
Differential
C7
Differential
-
Ground
D9
Differential
C9
Differential
-
Ground
D5
Differential
PIN74
B15_L16_N
PIN76
NC
PIN78
FPGA_TDI
PIN80
FPGA_TMS
CON1
Signal Name
Pin
NC
NC
NC
NC
PIN10
GND
PIN12
MGT_TX2_P
PIN14
MGT_TX2_N
PIN16
GND
PIN18
MGT_RX2_P
PIN20
MGT_RX2_N
PIN22
GND
PIN24
MGT_TX0_P
PIN26
MGT_TX0_N
PIN28
GND
PIN30
MGT_RX0_P
L18
3.3V
-
R13
3.3V
T13
3.3V
FPGA Pin Voltage
Level
-
NC
-
NC
-
NC
-
NC
-
Ground
B6
Differential
A6
Differential
-
Ground
B10
Differential
A10
Differential
-
Ground
B4
Differential
A4
Differential
-
Ground
B8
Differential
30 /
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