Alinx ARTIX-7FPGA User Manual page 37

Gigabit Ethernet Chip PHY1 pin assignments are as follows：
Signal Name
E1_GTXC
E1_TXD0
E1_TXD1
E1_TXD2
E1_TXD3
E1_TXEN
E1_RXC
E1_RXD0
E1_RXD1
E1_RXD2
E1_RXD3
E1_RXDV
E1_MDC
E1_MDIO
E1_RESET
Gigabit Ethernet Chip PHY2 pin assignments are as follows：
Signal Name
E2_GTXC
E2_TXD0
E2_TXD1
E2_TXD2
E2_TXD3
E2_TXEN
E2_RXC
E2_RXD0
E2_RXD1
E2_RXD2
E2_RXD3
E2_RXDV
E2_MDC
E2_MDIO
E2_RESET
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ARTIX-7 FPGA Development Board AX7203 User Manual
FPGA Pin Number
E18
C20
D20
A19
A18
F18
B17
A16
B18
C18
C19
A15
B16
B15
D16
FPGA Pin Number
A14
E17
C14
C15
A13
D17
E19
A20
B20
D19
C17
F19
F20
C22
B22
Description
PHY1 RGMII transmit clock
PHY1 Transmit Data bit0
PHY1 Transmit Data bit1
PHY1 Transmit Data bit2
PHY1 Transmit Data bit3
PHY1 Transmit Enable Signal
PHY1 RGMII Receive Clock
PHY1 Receive Data Bit0
PHY1 Receive Data Bit1
PHY1 Receive Data Bit2
PHY1 Receive Data Bit3
PHY1 receive data valid signal
PHY1 Management Clock
PHY1 Management Data
PHY1 Reset Signal
Description
PHY2 RGMII transmit clock
PHY2 Transmit Data bit0
PHY2 Transmit Data bit1
PHY2 Transmit Data bit2
PHY2 Transmit Data bit3
PHY2 Transmit Enable Signal
PHY2 RGMII Receive Clock
PHY2 Receive Data Bit0
PHY2 Receive Data Bit1
PHY2 Receive Data Bit2
PHY2 Receive Data Bit3
PHY2 receive data valid signal
PHY2 Management Clock
PHY2 Management Data
PHY2 Reset Signal
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