Part 2.8: Reset Button - Alinx ARTIX-7FPGA User Manual

Part 2.8: Reset Button

There is a reset button on the AC7200 FPGA core board. The reset button
is connected to the normal IO of the BANK34 of the FPGA chip. The user can
use this reset button to initialize the FPGA program. When the button is
pressed in the design, the signal voltage input to IO is low, and the reset signal
is valid; when the button is not pressed, the signal input to IO is high. The
schematic diagram of the reset button connection is shown:
Reset button pin assignment
Signal Name
RESET_N
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ARTIX-7 FPGA Development Board AX7203 User Manual
Reset Button Schematic
Reset button on the Core Board
ZYNQ Pin Name
IO_L17N_T2_34
ZYNQ Pin Number
T6
Description
FPGA system reset
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