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PCIex4 Interface Pin Assignment:
Signal Name
PCIE_RX0_P
PCIE_RX0_N
PCIE_RX1_P
PCIE_RX1_N
PCIE_RX2_P
PCIE_RX2_N
PCIE_RX3_P
PCIE_RX3_N
PCIE_TX0_P
PCIE_TX0_N
PCIE_TX1_P
PCIE_TX1_N
PCIE_TX2_P
PCIE_TX2_N
PCIE_TX3_P
PCIE_TX3_N
PCIE_CLK_P
PCIE_CLK_N
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ARTIX-7 FPGA Development Board AX7203 User Manual
Figure 3-3-2: PCIex4 on the Carrier board
FPGA Pin
D11
C11
B8
A8
B10
A10
D9
C9
D5
C5
B4
A4
B6
A6
D7
C7
F10
E10
Description
PCIE Channel 0 Data Receive Positive
PCIE Channel 0 Data Receive Negative
PCIE Channel 1 Data Receive Positive
PCIE Channel 1 Data Receive Negative
PCIE Channel 2 Data Receive Positive
PCIE Channel 2 Data Receive Negative
PCIE Channel 3 Data Receive Positive
PCIE Channel 3 Data Receive Negative
PCIE Channel 0 Data Transmit Positive
PCIE Channel 0 Data Transmit Negative
PCIE Channel 1 Data Transmit Positive
PCIE Channel 1 Data Transmit Negative
PCIE Channel 2 Data Transmit Positive
PCIE Channel 2 Data Transmit Negative
PCIE Channel 3 Data Transmit Positive
PCIE Channel 3 Data Transmit Negative
PCIE Reference Clock Positive
PCIE Reference Clock Negative
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