Part 3.12: Keys - Alinx ARTIX-7FPGA User Manual

XADC Pin Assignment
XADC
Interface
1，2
5，6
9，10

Part 3.12: keys

The AX7203 FPGA carrier board contains two user keys KEY1~KEY2. All
keys are connected to the normal IO of the FPGA. The key is active low. When
the key is pressed, the IO input voltage of the FPGA is low. When no key is
pressed, The IO input voltage of the FPGA is high. The circuit of the key part is
shown in Figure 3-12-1.
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ARTIX-7 FPGA Development Board AX7203 User Manual
Figure 3-11-2: XADC Connector Schematic
Figure 3-11-3: XADC Connector on the Carrier board
FPGA Pin Input amplitude
VP_0 : L10 Peak to peak 1V
VN_0 : M9
AD9P : J15 Peak to peak 1V
AD9N : H15
AD0P : H13 Peak to peak 1V
AD0N : G13
Description
FPGA-specific XADC input channel
FPGA-assisted XADC input channel 9
(can be used as normal IO)
FPGA-assisted XADC input channel 0
(can be used as normal IO)
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