Part 3.19: Dip Switch Configuration - Alinx ZYNQ UltraScale+ AXU9EGB User Manual

ZYNQ pin assignment of keys
Signal Name
PS_KEY1
PL_KEY1

Part 3.19: DIP Switch Configuration

There is a 4-digit DIP switch SW1 on the FPGA development board to
configure the startup mode of the ZYNQ system. The AXU9EGB system
development platform supports 4 startup modes. The 4 startup modes are
JTAG debug mode, QSPI FLASH, EMMC and SD2.0 card startup mode. After
ZU15EV chip is powered on, it will detect the level of (PS_MODE0~3) to
determine the startup mode. The user can select different startup modes
through the DIP switch SW1 on the expansion board. The SW1 startup mode
configuration is shown in the following table 3-19-1.
SW1
63 / 66
Figure 3-18-1: Rest keys connection diagram
ZYNQ Pin Name
PS_MIO26
B44_L1_N
Dial Position （1， 2， 3, 4）
ON，ON，ON，ON
AXU9EGB User Manual
ZYNQ Pin Number
H23
AN12
MODE[3:0]
0000
Description
PS KEY Input
PL KEY Input
Start mode
PS JTAG
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