Alinx ZYNQ UltraScale+ AXU9EGB User Manual page 16

highest operating speed of the DDR4 SDRAM on the PL side can reach
1200MHz (data rate 2400Mbps), and two piece of DDR4 is connected to the
BANK64,65 interface of the FPGA. The specific configuration of DDR4 SDRAM
is shown in Table 2-3-1 below:
Bit Number
U4,U5,U6,U7
The hardware design of DDR4 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR4.
The hardware connection of DDR4 SDRAM on the PS Side is shown in
Figure 2-3-1:
Figure 2-3-1: DDR3 DRAM schematic diagram
The hardware connection of DDR4 SDRAM on the Pl Side is shown in
Figure 2-3-2:
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Chip Model
MT40A512M16LY-062E
Table 2-3-1: DDR4 SDRAM Configuration
AXU9EGB User Manual
Capacity Factory
512M x 16bit
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Micron