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Figure 2-3-2: DDR4 DRAM schematic diagram
PS Side DDR4 DRAM pin assignment:
Signal Name
PS_DDR4_DQS0_N
PS_DDR4_DQS0_P
PS_DDR4_DQS1_N
PS_DDR4_DQS1_P
PS_DDR4_DQS2_N
PS_DDR4_DQS2_P
PS_DDR4_DQS3_N
PS_DDR4_DQS3_P
PS_DDR4_DQS4_N
PS_DDR4_DQS4_P
PS_DDR4_DQS5_N
PS_DDR4_DQS5_P
PS_DDR4_DQS6_N
PS_DDR4_DQS6_P
PS_DDR4_DQS7_N
PS_DDR4_DQS7_P
PS_DDR4_DQ0
PS_DDR4_DQ1
17 / 66
Pin Name
PS_DDR_DQS_N0_504
PS_DDR_DQS_P0_504
PS_DDR_DQS_N1_504
PS_DDR_DQS_P1_504
PS_DDR_DQS_N2_504
PS_DDR_DQS_P2_504
PS_DDR_DQS_N3_504
PS_DDR_DQS_P3_504
PS_DDR_DQS_N4_504
PS_DDR_DQS_P4_504
PS_DDR_DQS_N5_504
PS_DDR_DQS_P5_504
PS_DDR_DQS_N6_504
PS_DDR_DQS_P6_504
PS_DDR_DQS_N7_504
PS_DDR_DQS_P7_504
PS_DDR_DQ0_504
PS_DDR_DQ1_504
AXU9EGB User Manual
Pin Number
AN19
AN18
AN22
AN21
AJ19
AH19
AH23
AH22
AH29
AH28
AE29
AE28
AK32
AJ32
AE33
AE32
AP20
AP18
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