Part 3.14: Jtag Debug Port; Part 3.15: Real-Time Clock - Alinx ZYNQ UltraScale+ AXU9EGB User Manual

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Part 3.14: JTAG Debug Port

The JTAG interface is reserved on the AXU9EGB expansion board for
downloading ZYNQ UltraScale+ programs or firmware programs to FLASH. In
order to not damage the ZYNQ UltraScale+ chip by plugging and unplugging
under power, we aded a protection diode to the JTAG signal to ensure that the
signal voltage is within the range accepted by the FPGA and avoid damage to
the ZYNQ UltraScale+ chip.

Part 3.15: Real-time Clock

The ZU9EG chip has the function of an RTC real-time clock, with timing
functions such as year, month, day, hour, minute, and second, and week.
External need to connect a 32.768KHz passive clock to provide an accurate
clock source to the internal clock circuit, so that the RTC can accurately provide
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Figure 3-14-1: JTAG Interface Schematic
AXU9EGB User Manual
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