Alinx AXU2CGB-E User Manual
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Alinx AXU2CGB-E User Manual

Zynq ultrascale+ mpsoc fpga development board
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ZYNQ UltraScale+ MPSoC
FPGA Development Board
AXU2CGB-E
User Manual

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Summary of Contents for Alinx AXU2CGB-E

  • Page 1 ZYNQ UltraScale+ MPSoC FPGA Development Board AXU2CGB-E User Manual...

  • Page 2: Version Record

    AXU2CGB-E User Manual Version Record Version Date Release By Description Rev 1.0 2022-09-08 2 / 57 www.alinx.com...

  • Page 3: Table Of Contents

    AXU2CGB-E User Manual Table of Contents Version Record .....................2 Part 1: FPGA Development Board Introduction .......... 6 Part 2: ACU2CG core board ..............10 Part 2.1: ACU2CG core board Introduction ........10 Part 2.2: ZYNQ Chip ................11 Part 2.3: DDR4 DRAM ................13 Part 2.4: QSPI Flash ................18...
  • Page 4 Part 3.14: EEPROM and Temperature sensor ........51 Part 3.15: User LEDs ................52 Part 3.16: Keys ................... 53 Part 3.17: DIP Switch Configuration ...........54 Part 3.18: Power Supply ..............55 Part 3.19: ALINX Customized Fan ............. 56 Part 3.20: Carrier Board Size Dimension ...........57 4 / 57 www.alinx.com...
  • Page 5 AXU2CGB-E User Manual This MPSoCs FPGA development platform adopts the core board + carrier board mode, which is convenient for users to use the core board for secondary development. The core board uses XILINX Zynq UltraScale+ CEG chip ZU2CG solution, uses Processing System(PS)+Programmable Logic(PL) technology to integrate dual-core ARM ARM Cortex-A53 and FPGA programmable logic on a single chip.

  • Page 6: Part 1: Fpga Development Board Introduction

    AXU2CGB-E User Manual Part 1: FPGA Development Board Introduction The entire structure of the AXU2CGB-E FPGA development board is inherited from our consistent core board + carrier board model. A high-speed inter-board connector is used between the core board and the carrier board.
  • Page 7 AXU2CGB-E User Manual Figure 1-1-1: The Schematic Diagram of the AXU2CGB-E Through this diagram, you can see the interfaces and functions that the AXU2CGB-E FPGA Development Board contains:  ACU2CG core board It consists of ACU2CG +4GB DDR4 （PS） +8GB eMMC FLASH + 256Mb QSPI FLASH, and there are 2 crystal oscillators to provide the clock, a single-ended 33.3333MHz crystal oscillator for the PS system, and a...
  • Page 8  40-pin expansion port 2 40-pin 0.1-inch pitch expansion port can be connected to various ALINX modules (binocular camera, TFT LCD screen, high-speed AD module, etc.). The expansion port contains 1-channel 5V power supply, 2-channel 3.3V power supply, 3-channel way ground, 34 IOs port.
  • Page 9 AXU2CGB-E User Manual  JTAG debug port A 10-pin 0.1 spacing standard JTAG ports for FPGA program download and debugging. Users can debug and download the ZU2CG system through the XILINX downloader.  Temperature and humidity sensor chip LM75 On-board temperature and humidity sensor chip LM75, used to detect...

  • Page 10: Part 2: Acu2Cg Core Board

    AXU2CGB-E User Manual Part 2: ACU2CG core board Part 2.1: ACU2CG core board Introduction ACU2CG (core board model, the same below) FPGA core board, ZYNQ chip is based on XCZU2CG-1SFVC784E of XILINX company Zynq UltraScale+ MPSoCs CG series. This core board uses 4 Micron DDR4 chips MT40A512M16GE on the PS side, to form a 64-bit data bus bandwidth and 2GB capacity.

  • Page 11: Part 2.2: Zynq Chip

    AXU2CGB-E User Manual Figure 2-1-1: ACU2CG Core Board (Front View) Part 2.2: ZYNQ Chip The FPGA core board ACU2CG uses Xilinx's Zynq UltraScale+ MPSoCs CG series chip, module XCZU2CG-1SFVC784E. The PS system of the ZU2CG chip integrates 2 ARM Cortex™-A53 processors with a speed of up to 1.2Ghz and supports Level 2 Cache;...
  • Page 12 AXU2CGB-E User Manual Figure 2-2-1: Overall Block Diagram of the ZYNQ ZU2CG Chip The main parameters of the PS system part are as follows:  ARM quad-core Cortex ™ -A53 processor, speed up to 1.2GHz, each CPU 32KB level 1 instruction and data cache, 1MB level 2 cache, shared by 2 CPUs ...

  • Page 13: Part 2.3: Ddr4 Dram

    AXU2CGB-E User Manual  Static storage interface, support NAND, 2xQuad-SPI FLASH.  High-speed connection interface, support PCIe Gen2 x 4, 2 x USB3.0, Sata 3.1, Display Port, 4 x Tri-mode Gigabit Ethernet  Common connection interfaces: 2 x USB2.0, 2 x SD/SDIO, 2 x UART, 2 x CAN 2.0B, 2 x I2C, 2 x SPI, 4 x 32b GPIO...
  • Page 14 AXU2CGB-E User Manual are directly connected to the memory interface of the PS BANK504. The highest operating speed of the DDR4 SDRAM on the PL side can reach 1066MHz (data rate 2133Mbps), and four DDR4 storage systems are directly connected to the memory interface of PS's BANK504. The specific...
  • Page 15 AXU2CGB-E User Manual PS Side DDR4 DRAM pin assignment: Signal Name Pin Name Pin Number PS_DDR4_DQS0_P PS_DDR_DQS_P0_504 AF21 PS_DDR4_DQS0_N PS_DDR_DQS_N0_504 AG21 PS_DDR4_DQS1_P PS_DDR_DQS_P1_504 AF23 PS_DDR4_DQS1_N PS_DDR_DQS_N1_504 AG23 PS_DDR4_DQS2_P PS_DDR_DQS_P2_504 AF25 PS_DDR4_DQS2_N PS_DDR_DQS_N2_504 AF26 PS_DDR4_DQS3_P PS_DDR_DQS_P3_504 AE27 PS_DDR4_DQS3_N PS_DDR_DQS_N3_504 AF27 PS_DDR4_DQS4_P...
  • Page 16 AXU2CGB-E User Manual PS_DDR4_DQ16 PS_DDR_DQ16_504 AC26 PS_DDR4_DQ17 PS_DDR_DQ17_504 AD26 PS_DDR4_DQ18 PS_DDR_DQ18_504 AD25 PS_DDR4_DQ19 PS_DDR_DQ19_504 AD24 PS_DDR4_DQ20 PS_DDR_DQ20_504 AG26 PS_DDR4_DQ21 PS_DDR_DQ21_504 AH25 PS_DDR4_DQ22 PS_DDR_DQ22_504 AH26 PS_DDR4_DQ23 PS_DDR_DQ23_504 AG25 PS_DDR4_DQ24 PS_DDR_DQ24_504 AH27 PS_DDR4_DQ25 PS_DDR_DQ25_504 AH28 PS_DDR4_DQ26 PS_DDR_DQ26_504 AF28 PS_DDR4_DQ27 PS_DDR_DQ27_504 AG28 PS_DDR4_DQ28...
  • Page 17 AXU2CGB-E User Manual PS_DDR4_DQ51 PS_DDR_DQ51_504 PS_DDR4_DQ52 PS_DDR_DQ52_504 PS_DDR4_DQ53 PS_DDR_DQ53_504 PS_DDR4_DQ54 PS_DDR_DQ54_504 PS_DDR4_DQ55 PS_DDR_DQ55_504 PS_DDR4_DQ56 PS_DDR_DQ56_504 PS_DDR4_DQ57 PS_DDR_DQ57_504 PS_DDR4_DQ58 PS_DDR_DQ58_504 PS_DDR4_DQ59 PS_DDR_DQ59_504 PS_DDR4_DQ60 PS_DDR_DQ60_504 PS_DDR4_DQ61 PS_DDR_DQ61_504 PS_DDR4_DQ62 PS_DDR_DQ62_504 PS_DDR4_DQ63 PS_DDR_DQ63_504 PS_DDR4_DM0 PS_DDR_DM0_504 AG20 PS_DDR4_DM1 PS_DDR_DM1_504 AE23 PS_DDR4_DM2 PS_DDR_DM2_504 AE25 PS_DDR4_DM3 PS_DDR_DM3_504...

  • Page 18: Part 2.4: Qspi Flash

    AXU2CGB-E User Manual PS_DDR4_WE_B PS_DDR_A14_504 AB24 PS_DDR4_CAS_B PS_DDR_A15_504 AC24 PS_DDR4_RAS_B PS_DDR_A16_504 AC23 PS_DDR4_ACT_B PS_DDR_ACT_N_504 PS_DDR4_ALERT_B PS_DDR_ALERT_N_504 PS_DDR4_BA0 PS_DDR_BA0_504 PS_DDR4_BA1 PS_DDR_BA1_504 PS_DDR4_BG0 PS_DDR_BG0_504 PS_DDR4_CS0_B PS_DDR_CS_N0_504 PS_DDR4_ODT0 PS_DDR_ODT0_504 PS_DDR4_PARITY PS_DDR_PARITY_504 PS_DDR4_RESET_B PS_DDR_RST_N_504 PS_DDR4_CLK0_P PS_DDR_CK0_P_504 PS_DDR4_CLK0_N PS_DDR_CK0_N_504 PS_DDR4_CKE0 PS_DDR_CKE0_504 Part 2.4: QSPI Flash...

  • Page 19: Part 2.5: Emmc Flash

    AXU2CGB-E User Manual 2-4-1 shows the QSPI Flash in the schematic. Figure 2-4-1: QSPI Flash in the schematic Configure chip pin assignments: Signal Name Pin Name Pin Number MIO0_QSPI0_SCLK PS_MIO0_500 AG15 MIO1_QSPI0_IO1 PS_MIO1_500 AG16 MIO2_QSPI0_IO2 PS_MIO2_500 AF15 MIO3_QSPI0_IO3 PS_MIO3_500 AH15...
  • Page 20 AXU2CGB-E User Manual Position Model Capacity Factory FEMDRM008G-58A39 8G Byte FORESEE Table 2-5-1: eMMC FLASH Specification The eMMC FLASH is connected to the GPIO port of the BANK500 of the PS part of the ZYNQ UltraScale+. In the system design, it is necessary to configure the GPIO port function of the PS side as an EMMC interface.

  • Page 21: Part 2.6: Clock Configuration

    AXU2CGB-E User Manual MMC_CCLK PS_MIO22_500 AB20 MMC_RSTN PS_MIO23_500 AB18 Part 2.6: Clock configuration The core board provides reference clock and RTC real-time clock for PS system and PL logic respectively, so that PS system and PL logic can work independently. The schematic diagram of the clock circuit design is shown in...
  • Page 22 AXU2CGB-E User Manual Clock pin assignment: Signal Name PS_PADI_503 PS_PADO_503 PS System Clock Source The X1 crystal on the core board provides a 33.333MHz clock input for the PS part. The clock input is connected to the PS_REF_CLK_503 pin of BANK503 of the ZYNQ chip.

  • Page 23: Part 2.7: Led

    AXU2CGB-E User Manual Figure 2-6-4: PL system clock source Clock pin assignment: Signal Name PL_CLK0_P PL_CLK0_N Part 2.7: LED There is a red power indicator (PWR) and a configuration LED (DONE) on the ACU2CG core board. When the core board is powered on, the power indicator will light up;...

  • Page 24: Part 2.8: Power Supply

    AXU2CGB-E User Manual Part 2.8: Power Supply The power supply voltage of the ACU2CG core board is DC12V, which is supplied by connecting the carrier board. The core board uses a PMIC chip TPS6508641 to generate all the power required by the XCZU2CG chip. For the TPS6508641 power supply design, please refer to the power supply chip manual.

  • Page 25: Part 2.9: Acu2Cg Core Board Form Factor

    AXU2CGB-E User Manual In addition, the VCCIO power supply of BANK65 and BANK66 of XCZU2CG chip is provided by the carrier board, which is convenient for users to modify, but the maximum power supply cannot exceed 1.8V. Part 2.9: ACU2CG Core Board Form Factor Figure 2-9-1: ACU2CG Core Board Form Factor Part 2.10: Board to Board Connectors pin assignment...
  • Page 26 AXU2CGB-E User Manual them, J29 is connected to the IO of BANK65 and BANK66, J30 is connected to the IO of BANK25, BANK26, BANK66 and the transceiver signal of BANK505 MGT, J31 is connected to the IO of BANK24 and BANK44, J32 is connected to the MIO, VCCO_65, VCCO_66 and +12V power supply of PS.
  • Page 27 AXU2CGB-E User Manual B65_L14_N B65_L19_N B65_L5_N B65_L18_P B65_L5_P B65_L18_N B65_L11_N B65_L8_P B65_L11_P B65_L8_N B65_L10_N B65_L24_N B65_L10_P B65_L24_P B66_L3_P B65_L12_P B66_L3_N B65_L12_N B66_L1_P B65_L13_N B66_L1_N B65_L13_P B66_L6_P B65_L21_P B66_L6_N B65_L21_N B66_L16_P B65_L23_P B66_L16_N B65_L23_N B66_L15_P B66_L5_N B66_L15_N B66_L5_P B66_L4_P B66_L2_P B66_L4_N...
  • Page 28 AXU2CGB-E User Manual B66_L12_P B66_L7_P B66_L12_N B66_L7_N B66_L13_N B66_L10_P B66_L13_P B66_L10_N B66_L8_N B66_L9_P B66_L8_P B66_L9_N Pin assignment of board to board connector J30 J30 Pin Signal Name Pin Number J30 Pin Signal Name Pin Number B66_L14_P FPGA_TDI B66_L14_N FPGA_TCK B66_L22_P...
  • Page 29 AXU2CGB-E User Manual B66_L18_P B25_L12_N B25_L4_N B25_L11_P B25_L4_P B25_L11_N B26_L11_P B25_L6_N B26_L11_N B25_L6_P B26_L10_N B26_L6_N B26_L10_P B26_L6_P B26_L7_N B26_L3_N B26_L7_P B26_L3_P B26_L9_N B26_L2_N B26_L9_P B26_L2_P B26_L5_N B26_L4_N B26_L5_P B26_L4_P B26_L1_P B26_L12_P B26_L1_N B26_L12_N 505_CLK2_P 505_CLK1_P 505_CLK2_P 505_CLK1_P 505_CLK0_P 505_CLK3_P 505_CLK0_N...
  • Page 30 AXU2CGB-E User Manual 505_RX3_P 505_TX0_P 505_RX3_N 505_TX0_N 505_TX2_P 505_RX1_P 505_TX2_N 505_RX1_N 505_RX2_P 505_RX0_P 505_RX2_N 505_RX0_N Pin assignment of board to board connector J31 J31 Pin Signal Name Pin Number J31 Pin Signal Name Pin Number B24_L10_P B24_L7_P AA13 B24_L10_N B24_L7_N...
  • Page 31 AXU2CGB-E User Manual B44_L12_P AB10 B44_L9_N AA10 B44_L10_N B44_L3_P AH12 B44_L10_P B44_L3_N AH11 B24_L11_N B44_L1_N AH10 B24_L11_P B44_L1_P AG10 B24_L9_N B24_L4_P AE13 B24_L9_P B24_L4_N AF13 B24_L8_P AB15 B44_L5_P AE12 B24_L8_N AB14 B44_L5_N AF12 B44_L2_N AG11 B44_L4_N AF10 B44_L2_P AF11 B44_L4_P...
  • Page 32 AXU2CGB-E User Manual 224_RX2_P 224_TX2_P 224_RX2_N 224_TX2_N 224_RX1_P 224_TX1_P 224_RX1_N 224_TX1_N 224_RX0_P 224_TX0_P 224_RX0_N 224_TX0_N Pin assignment of board to board connector J32 J32 Pin Signal Name Pin Number J32 Pin Signal Name Pin Number PS_MIO35 PS_MIO30 PS_MIO29 PS_MIO31 PS_MIO58...
  • Page 33 AXU2CGB-E User Manual PS_MIO61 PS_MIO39 PS_MIO62 PS_MIO38 PS_MIO63 PS_MIO65 PS_MIO40 PS_MIO66 PS_MIO44 PS_MIO67 PS_MIO45 PS_MIO68 PS_MIO47 PS_MIO64 PS_MIO48 PS_MIO69 PS_MIO41 PS_MIO74 PS_MIO32 PS_MIO73 PS_MIO46 PS_MIO72 PS_MIO50 PS_MIO71 PS_MIO49 PS_MIO75 PS_MIO34 PS_MIO70 PS_MIO26 PS_MIO43 PS_MIO24 AB19 PS_MIO51 PS_MIO25 AB21 PS_MIO42 PS_MIO33...
  • Page 34 AXU2CGB-E User Manual VCCO_65 VCCO_66 +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V 34 / 57 www.alinx.com...

  • Page 35: Part 3: Carrier Board

    AXU2CGB-E User Manual Part 3: Carrier Board Part 3.1: Carrier Board Introduction Through the previous function introduction, you can understand the function of the carrier board part  1-Channel M.2 interface  1-Channel DP output interface  4 USB 3.0 Interfaces ...

  • Page 36: Part 3.2: M.2 Interface

     3 Keys Part 3.2: M.2 Interface The AXU2CGB-E development board is equipped with a PCIE x1 standard M.2 interface for connecting M.2 SSD solid state drives, with a communication speed of up to 6Gbps. The M.2 interface uses the M key slot, which only supports PCI-E, not SATA.

  • Page 37: Part 3.3: Dp Interface

    PS_MIO37_501 PCIE Reset Signal Part 3.3: DP Interface The AXU2CGB-E development board has a standard DisplayPort output display interface for video image display. The interface supports VESA DisplayPort V1.2a output standard, up to 4K x 2K@30Fps output, supports Y-only, YCbCr444, YCbCr422, YCbCr420 and RGB video formats, each color supports 6, 8, 10, or 12 bits.
  • Page 38 AXU2CGB-E User Manual Figure 3-3-1: DP interface design Schematic The DisplayPort interface ZYNQ pin assignment is as follows: Signal Name ZYNQ Pin Number ZYNQ Pin Number Description Low bits of DP Data GT0_DP_TX_P 505_TX3_P Transmit Positive Low bits of DP Data...

  • Page 39: Part 3.4: Usb3.0 Interface

    AXU2CGB-E User Manual Part 3.4: USB3.0 interface There are 4 USB3.0 ports on the AXU2CGB-E carrier board, supporting the HOST working mode, and the data transmission speed is up to 5.0Gb/s. USB3.0 is connected through the PIPE3 interface, and USB2.0 is connected to the external USB3320C chip through the ULPI interface to realize high-speed USB3.0 and USB2.0 data communication.

  • Page 40: Part 3.5: Gigabit Ethernet Interface

    USB2.0 Reset Signal Part 3.5: Gigabit Ethernet Interface There are 2 Gigabit Ethernet ports on the AXU2CGB-E carrier board, one is connected to the PS end, and the other is connected to the PL end. The GPHY chip uses JLSemi JL2121-N040I Ethernet GPHY chip to provide users with network communication services.
  • Page 41 AXU2CGB-E User Manual RXCTL_ADR2 TX clock 2ns delay delay RXD1_TXDLY delay RXD0_RXDLY RX clock 2ns delay Table 3-5-1: PHY chip default configuration value When the network is connected to Gigabit Ethernet, the data transmission of ZYNQ and PHY chip JL2121-N040I is communicated through the RGMII bus, the transmission clock is 125Mhz, and the data is sampled on the rising edge and falling samples of the clock.

  • Page 42: Part 3.6: Usb To Serial Port

    Ethernet 2 Reset Signal Part 3.6: USB to Serial Port The AXU2CGB-E carrier board is equipped with two Uart to USB ports, one is connected to the PS end, and one is connected to the PL end. The conversion chip uses Silicon Labs CP2102GM's USB-UAR chip, and 42 / 57 www.alinx.com...

  • Page 43: Part 3.7: Sd Card Slot Interface

    PL Uart Data Input Part 3.7: SD Card Slot Interface The AXU2CGB-E FPGA Development Board contains a Micro SD card interface to provide user access to the SD card memory, the BOOT program for the ZU2CG chip, the Linux operating system kernel, the file 43 / 57 www.alinx.com...

  • Page 44: Part 3.8: Expansion Header

    Part 3.8: Expansion Header The AXU2CGB-E board is reserved with two 0.1-inch standard pitch 40-pin expansion ports J45 and J46, which are used to connect the ALINX modules or the external circuit designed by the user. The expansion port has 40 signals, of 44 / 57 www.alinx.com...
  • Page 45 AXU2CGB-E User Manual which 1-channel 5V power supply, 2-channel 3.3 V power supply, 3-channle Do not directly connect the IO directly to the 5V device ground and 34 IOs. to avoid burning the FPGA. If you want to connect 5V equipment, you need to connect level conversion chip.

  • Page 46: Part 3.9: Can Communication Interface

    +3.3V Part 3.9: CAN communication interface There are 2 CAN communication interfaces on the AXU2CGB-E carrier board, which are connected to the MIO interface of the BANK501 on the PS system side. The CAN transceiver chip selected TI's SN65HVD232C chip for user CAN communication services.

  • Page 47: Part 3.10: 485 Communication Interface

    CAN2 Transmitter Part 3.10: 485 communication interface There are two 485 communication interfaces on the AXU2CGB-E carrier board. The 485 communication port 1 is connected to the IO interface of BANK43~45 on the PL system. The 485 transceiver chip selects the MAX3485 chip from MAXIM for the user's 485 communication service.

  • Page 48: Part 3.11: Mipi Camera Interface

    Part 3.11: MIPI camera interface The AXU2CGB-E carrier board includes a MIPI camera interface, which can be used to connect with the ALINX Brand MIPI OV5640 camera module AN5641. MIPI interface 15PIN FPC connector, 2 LANE data and 1 pair of clock, connected to the differential IO pin of BANK65, the level standard is 1.2V;...

  • Page 49: Part 3.12: Jtag Debug Port

    GPIO Control of Camera CAM_CLK B43_L4_N AF10 Clock Input of Camera CAM_SCL B43_L11_P I2C Clock of Camera CAM_SDA B43_L11_N I2C Data of Camera Part 3.12: JTAG Debug Port The JTAG interface is reserved on the AXU2CGB-E expansion board for 49 / 57 www.alinx.com...

  • Page 50: Part 3.13: Real-Time Clock

    AXU2CGB-E User Manual downloading ZYNQ UltraScale+ programs or firmware programs to FLASH. In order to not damage the ZYNQ UltraScale+ chip by plugging and unplugging under power, we aded a protection diode to the JTAG signal to ensure that the signal voltage is within the range accepted by the FPGA and avoid damage to the ZYNQ UltraScale+ chip.

  • Page 51: Part 3.14: Eeprom And Temperature Sensor

    PS terminal through the IIC bus. A high-precision, low-power, digital temperature sensor chip is installed on the AXU2CGB-E FPGA development board, and the model is LM75 from ON Semiconductor. The temperature accuracy of the LM75 chip is 0.5 degrees.

  • Page 52: Part 3.15: User Leds

    IIC Data Signal Part 3.15: User LEDs There are 3 LEDs on the AXU2CGB-E Carrier board. including 1 power indicator light, 1 User LED Controlled by PS side, and 1 User LED Controlled by PL side. The user can control the user LED on and off through the program.

  • Page 53: Part 3.16: Keys

    User LED controlled by PL Part 3.16: Keys There are 1 reset KEY RESET and 2 user buttons on the AXU2CGB-E carrier board. The reset signal is connected to the reset chip input of the core board ACU3EG, and the user can use this reset KEY to reset the ZYNQ system.

  • Page 54: Part 3.17: Dip Switch Configuration

    Part 3.17: DIP Switch Configuration There is a 4-digit DIP switch SW1 on the FPGA development board to configure the startup mode of the ZYNQ system. The AXU2CGB-E system development platform supports 4 startup modes. The 4 startup modes are JTAG debug mode, QSPI FLASH, EMMC and SD2.0 card startup mode.

  • Page 55: Part 3.18: Power Supply

    Table 3-17-1 Part 3.18: Power Supply The power input voltage of the AXU2CGB-E development board is DC12V. In the carrier board, the DC12V is converted into +5V, +3.3V, and +1.8V through one-way DC/DC power chip TPS54620 and two-way DC/DC power chip MP1482.

  • Page 56: Part 3.19: Alinx Customized Fan

    BANK65 of Core Board Part 3.19: ALINX Customized Fan Because AXU2CGB-E generates a lot of heat when it works normally, we add a heat sink and fan to the chip on the board to prevent the chip from overheating. The control of the fan is controlled by the ZYNQ chip. The control pin is connected to the IO of the BANK43 (AA11).

  • Page 57: Part 3.20: Carrier Board Size Dimension

    AXU2CGB-E User Manual Figure 3-19-1：Fan Design Schematic The fan has been screwed to the AXU2CGB-E FPGA development board before leaving the factory. The power of the fan is connected to the socket of J24. The red is positive and the black is negative.

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