Alinx ZYNQ UltraScale+ AXU9EGB User Manual page 45

Fpga development board
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Figure 3-5-1: ZYNQ PS system and GPHY connection diagram
PS Gigabit Ethernet pin assignment is as follows
Signal Name
PHY1_TXCK
PHY1_TXD0
PHY1_TXD1
PHY1_TXD2
PHY1_TXD3
PHY1_TXCTL
PHY1_RXCK
PHY1_RXD0
PHY1_RXD1
PHY1_RXD2
PHY1_RXD3
PHY1_RXCTL
PHY1_MDC
PHY1_MDIO
PL Gigabit Ethernet pin assignment is as follows
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Pin Name
Pin Number
PS_MIO64
PS_MIO65
PS_MIO66
PS_MIO67
PS_MIO68
PS_MIO69
PS_MIO70
PS_MIO71
PS_MIO72
PS_MIO73
PS_MIO74
PS_MIO75
PS_MIO76
PS_MIO77
AXU9EGB User Manual
A25
Ethernet 1 RGMII Transmit Clock
A26
Ethernet 1 Transmit data bit0
A27
Ethernet 1 Transmit data bit1
B25
Ethernet 1 Transmit data bit2
B26
Ethernet 1 Transmit data bit3
B27
Ethernet 1 Transmit Enable Signal
C26
Ethernet 1 RGMII Receive Clock
C27
Ethernet 1 Receive Data Bit0
E25
Ethernet 1 Receive Data Bit1
H24
Ethernet 1 Receive Data Bit2
G25
Ethernet 1 Receive Data Bit3
D25
Ethernet 1 Receive Enable Signal
H25
Ethernet 1 MDIO Clock Management
F25
Ethernet 1 MDIO Management Data
Description
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