Part 3.5: Gigabit Ethernet Interface - Alinx ZYNQ UltraScale+ AXU9EGB User Manual

USB Interface Pin Assignment:
Signal Name
USB_SSTXP
USB_SSTXN
USB_SSRXP
USB_SSRXN
USB_DATA0
USB_DATA1
USB_DATA2
USB_DATA3
USB_DATA4
USB_DATA5
USB_DATA6
USB_DATA7
USB_STP
USB_DIR
USB_CLK
USB_NXT
USB_RESET_N

Part 3.5: Gigabit Ethernet Interface

There are 2 Gigabit Ethernet ports on the AXU9EGB carrier board, one is
connected to the PS end, and the other is connected to the PL end. The GPHY
chip uses JLSemi JL2121-N040IRNX Ethernet PHY chip to provide users with
network communication services. The Ethernet PHY chip on the PS side is
connected to the MIO interface of the BANK502 of the PS side of ZYNQ. The
Ethernet PHY chip on the PL side is connected to the IO of the BANK66. The
JL2121-N040I chip supports 10/100/1000 Mbps network transmission rate, and
communicates with the MAC layer of the ZU9EG system through the RGMII
interface. JL2121-N040I supports MDI/MDX adaptation, various speed
adaptation, Master/Slave adaptation, and MDIO bus for PHY register
management.
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Pin Name Pin Number
505_TX1_P Y29
505_TX1_N Y30
505_RX1_P AA31
505_RX1_N AA32
PS_MIO56 C23
PS_MIO57 A23
PS_MIO54 F23
PS_MIO59 B24
PS_MIO60 E24
PS_MIO61 C24
PS_MIO62 G24
PS_MIO63 D24
PS_MIO58 G23
PS_MIO53 E23
PS_MIO52 F22
PS_MIO55 B23
PS_MIO32 H22
AXU9EGB User Manual
Description
USB3.0 Data Transmit Positive
USB3.0 Data Transmit Negative
USB3.0 Data Receive Positive
USB3.0 Data Receive Negative
USB2.0 Data Bit0
USB2.0 Data Bit1
USB2.0 Data Bit2
USB2.0 Data Bit3
USB2.0 Data Bit4
USB2.0 Data Bit5
USB2.0 Data Bit6
USB2.0 Data Bit7
USB2.0 Stop Signal
USB2.0 Data Direction Signal
USB2.0 Clock Signal
USB2.0 Next Data Signal
USB2.0 Reset Signal
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