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S1R72104 Technical Manual
3. BLOCK DIAGRAM
Port interface section
XPDREQ
XPDACK
XPRD
XPWR
PD15-0
Clock control
2 Multiplying PLL
Clock distribution
2
Master mode control
Slave mode control
Bus control
DMA control
section
Start-up/stop control
section
SCSI-2(3) interface section
Command
analysis and
execution
FIFO
(16Byte)
FIFO control
DMA control
CPU interface
section
Data MPX
Timing control
Interrupt control
EPSON
Sequence
control
Phase
control
Parity
GEN/CHK
Asynchro-
nous transfer
control
Synchronous
transfer
SCAM
control
Internal
register
XSRST
XSATN
XSBSY
XSIO
XSCD
XSMSG
XSSEL
XSDB7-0
XSDP
XSREQ
XSACK
Rev.1.1
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