System Architecture - Analog Devices EZ-Board ADSP-BF518F Manual

System Architecture

System Architecture
This section describes the processor's configuration on the EZ-Board
(Figure 2-1).
IDC Conn
14 Pin 0.1
National
Semiconductor
DP83848
3.3 Volts
RJ45
16 Mb
SPI Flash
3.3 Volts
Figure 2-1. System Architecture
This EZ-Board is designed to demonstrate the ADSP-BF518F Blackfin
processor capabilities. The processor has an I/O voltage of 3.3V. The core
voltage of the processor is controlled by an Analog Devices ADP1715 low
dropout regulator (LDO) and an Analog Devices AD5258 digipot, which
2-2
64 MB
SDRAM
(32M x 16)
32.768 KHz
3.3 Volts
Oscillator
3.3 volt
RTC
High Speed I/O
Note: See the NGEI
Secification for a
complete understanding
of I/O provided with this
product
ADSP-BF518F
Processor
176-lead LQFP
UARTs CLKIN SPI
25 MHz
RS-232
Oscillator
TX/RX
3.3 Volts
3.3 Volts
RS-232
Female
Mic Aud
In In
ADSP-BF518F EZ-Board Evaluation System Manual
4 MB
Flash
(2M x 16 )
3.3 Volts
Connector
EBIU
400 MHz
SPORT TWI SPORT
12 bit
3 Channel A/D
AD7266
SSM2603
Codec
3.3 Volts
Inputs
6 Diff
12 SE
12 MHz
Head Aud
Oscillator
Out Out
3.3 Volts
SD
eMMC
RSI
2GB
Rotary
3.3 Volts
LEDs (3)
3.3 Volts
PBs (2)
3.3 Volts
or