Sdram Interface - Analog Devices EZ-Board ADSP-BF518F Manual

SDRAM Interface

Table 1-1. EZ-Board Internal Memory Map (Cont'd)
Start Address
0xFFB0 1000
0xFFC0 0000
0xFFE0 0000
Table 1-2. EZ-Board External Memory Map
Start Address
0x0000 0000
0x0800 0000
0x2000 0000
0x2010 0000
0x2020 0000
0x2030 0000
0x2040 0000
SDRAM Interface
The ADSP-BF518F processor connects to a 64 MB Micron
MT48LC32M16A2TG-75 chip through the external bus interface unit
(EBIU). The SDRAM chip can operate at a maximum clock frequency of
80 MHz, which is the ADSP-BF518F processor limitation.
With a VisualDSP++ session running and connected to the EZ-Board via
the USB standalone debug agent, the SDRAM registers are configured
automatically each time the processor is reset. The values are used when-
ever SDRAM is accessed through the debugger (for example, when
viewing memory windows or loading a program).
1-10
Content
Reserved
SYSTEM MMR REGISTERS
CORE MMR REGISTERS
End Address
0x03FF FFFF
0x1FFF FFFF
0x200F FFFF
0x201F FFFF
0x202F FFFF
0x203F FFFF
0xEEFF FFFF
ADSP-BF518F EZ-Board Evaluation System Manual
Content
SDRAM (SDRAM)
Reserved
ASYNC memory bank 0 (flash)
ASYNC memory bank 1 (flash)
ASYNC memory bank 2 (flash)
ASYNC memory bank 3 (flash)
Reserved