Flash Wp Jumper (Jp3); Otp Flag Enable Jumper (Jp14) - Analog Devices EZ-Board ADSP-BF518F Manual

Flash WP Jumper (JP3)

The flash WP jumper (
lel flash chip. Block 70 contains 64 KB of configuration data at address
range
0x203 F0000—0x203 FFFFF
and the parallel flash driver from Analog Devices is used, block 70 is
read-only. By default,

OTP Flag Enable Jumper (JP14)

The OTP flag enable jumper (
regulator. By default,
allows OTP writes.
must be installed for OTP writes to be successful. The nominal 2.5V
JP14
for OTP is temporarily raised to 7V when
taken when using the
extended amount of time.
There is a limited amount of time 7V can be applied to the proces-
sor's OTP interface. Violating the specifications listed in the
ADSP-BF512/ADSP-BF514/ADSP-BF516/ADSP-BF518 Blackfin
Embedded Processor data sheet can damage the processor.
Configured properly,
shut-down pin of the ADP1611 switching converter. Refer to the
ADSP-BF51x Blackfin Processor Hardware Reference Manual and the
ADSP-BF512/ADSP-BF514/ADSP-BF516/ADSP-BF518 Blackfin Embed-
ded Processor data sheet for more information about OTP writes.
ADSP-BF518F EZ-Board Evaluation System Manual
ADSP-BF518F EZ-Board Hardware Reference
) is used to write-protect block 70 of the paral-
JP3
. When the jumper is installed on
is installed.
JP3
) controls the precise 7V OTP voltage
JP14
is not installed; when installed, the jumper
JP14
signal in order to avoid driving 7V for an
OTP_FLAG
connects the processor's
JP14
is set high. Care must be
PH3
flag pin to the
PH3
,
JP3
2-15