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To disable the automatic setting of the SDRAM registers, select Target
Options from the Settings menu in VisualDSP++ and uncheck Use XML
reset values. For more information on changing the reset values, refer to
the online Help.
An example program is included in the EZ-Board installation directory to
demonstrate how to setup and access the SDRAM interface. For more
information on how to initialize the registers after a reset, search the Visu-
alDSP++ online Help for "reset values".
Parallel Flash Memory Interface
The parallel flash memory interface of the ADSP-BF518F EZ-Board con-
tains a 4 MB (2M x 16 bits) Numonyx M29W320EB chip. Flash memory
connects to the 16-bit data bus and address lines 1 through 19. Chip
enable is decoded by the
gates. The address range for flash memory is
Flash memory is pre-loaded with boot code for the power-on-self test
(POST) program. For more information, refer to
on page
1-23. Flash memory also is preloaded with configuration flash
information, which contains board revision, BOM revision, and other
data.
By default, the EZ-Board boots from the 16-bit parallel flash memory.
The processor boots from flash memory if the boot mode select switch
(
) is set to position 1 (see
SW1
page
2-8).
Flash memory code can be modified. For instructions, refer to the online
Help and example program included in the EZ-Board installation
directory.
For more information about the parallel flash device, refer to the Num-
onyx Web site:
ADSP-BF518F EZ-Board Evaluation System Manual
select lines through NAND and AND
AMS0—3
"Boot Mode Select Switch (SW1)" on
http://www.numonyx.com/
Using ADSP-BF518F EZ-Board
0x2000 0000
"Power-On-Self Test"
.
to
.
0x203F FFFF
1-11
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