Part 16: Keys - Alinx AXKU040 User Manual

Part 16: Keys

The AXKU040 FPGA development board contains two user Keys and 1
reset key. Two user keys are connected to the IO of FPGA BANK65.The user
key is active at low level to realize some functions of the board for customers;
The reset key is connected to FPGA BANK64 for system reset.
The circuit of user key part is shown in Figure 16-1.
Keys Pin Assignment
Signal Name
KEY1
KEY2
FPGA_RSETn
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KINTEX UltraScale+ FPGA Board AXKU040 User Manual
Figure 16-1: Keys Schematic
FPGA Pin
IO_L13N_T2L_N1_GC_QBC_44
IO_L24P_T3U_N10_EMCCLK_65
IO_L24P_T3U_N10_64
FPGA Pin
Number
K21
K20
AK8
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Description
User Key Input
User Key Input
System Reset