Alinx AXKU040 User Manual page 25

Figure 9-1: FPGA Chip and GPHY connection diagram
The 1 Gigabit Ethernet interface pin assignments are as follows:
st
Signal Name
PHY1_GTXC IO_L4N_T0U_N7_DBC_AD7N_66
PHY1_TXD0 IO_L14N_T2L_N3_GC_66
PHY1_TXD1
PHY1_TXD2
PHY1_TXD3 IO_L4P_T0U_N6_DBC_AD7P_66
PHY1_TXEN IO_L21N_T3L_N5_AD8N_66
PHY1_RXC IO_L14P_T2L_N2_GC_66
PHY1_RXD0
PHY1_RXD1 IO_L20N_T3L_N3_AD1N_66
PHY1_RXD2
PHY1_RXD3 IO_L21P_T3L_N4_AD8P_66
PHY1_RXDV IO_L20P_T3L_N2_AD1P_66
PHY1_MDC
PHY1_MDIO
PHY1_RESET
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KINTEX UltraScale+ FPGA Board AXKU040 User Manual
Pin Name
IO_L2P_T0L_N2_66
IO_L2N_T0L_N3_66
IO_L23P_T3U_N8_66
IO_L23N_T3U_N9_66
IO_T2U_N12_66
IO_T3U_N12_66
IO_T1U_N12_66
Pin
Number
A10 Ethernet 1 Transmit Clock
G12 Ethernet 1 Transmit Data bit0
B9 Ethernet 1 Transmit Data bit1
A9 Ethernet 1 Transmit Data bit2
B10 Ethernet 1 Transmit Data bit3
Ethernet 1 Transmit Enable
B11
H12 Ethernet 1 Receive Clock
A13 Ethernet 1 Receive Data Bit0
B12 Ethernet 1 Receive Data Bit1
A12 Ethernet 1 Receive Data Bit2
C11 Ethernet 1 Receive Data Bit3
Ethernet 1 Receive Data Enable
C12
Ethernet 1 MDIO Management
F12
Ethernet 1 MDIO Management
E12
L9
Description
Signal
Signal
Clock
Data
Ethernet Chip Reset
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