Part 14: Jtag Interface - Alinx AXKU040 User Manual

Part 14: JTAG Interface

A JTAG interface is reserved JTAG interface one the AXKU040 FPGA
development board for downloading FPGA programs or firmware to FLASH. In
order to prevent damage to the FPGA chip caused by hot plugging, a protection
diode is added to the JTAG signal to ensure that the voltage of the signal is
within the range accepted by the FPGA to avoid damage of the FPGA chip.
JTAG Pin Assignment
Signal Name FPGA
Pin
FPGA_TDI TDI_0
FPGA_TMS TMS_0
FPGA_TDO TDO_0
FPGA_TCK TCK_0
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KINTEX UltraScale+ FPGA Board AXKU040 User Manual
Figure 14-1: JTAG Interface Schematic
FPGA Pin
Number
V9
W9
U9
AC9
Description
JTAG Data Input Pin
JTAG Control Pin
JTAG Data Output Pin
JTAG Clock Pin
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