Alinx AXKU040 User Manual page 26

The 2 Gigabit Ethernet interface pin assignments are as follows:
nd
Signal Name
IO_L10P_T1U_N6_QBC_AD4P
PHY2_GTXC
PHY2_TXD0 IO_L17P_T2U_N8_AD10P_67
PHY2_TXD1 IO_L17N_T2U_N9_AD10N_67
PHY2_TXD2 IO_L15P_T2L_N4_AD11P_67
PHY2_TXD3 IO_L15N_T2L_N5_AD11N_67
IO_L10N_T1U_N7_QBC_AD4N
PHY2_TXEN
IO_L13P_T2L_N0_GC_QBC_6
PHY2_RXC
IO_L4P_T0U_N6_DBC_AD7P_
PHY2_RXD0
PHY2_RXD1 IO_L6N_T0U_N11_AD6N_67
PHY2_RXD2 IO_L6P_T0U_N10_AD6P_67
IO_L13N_T2L_N1_GC_QBC_6
PHY2_RXD3
IO_L4N_T0U_N7_DBC_AD7N_
PHY2_RXDV
PHY2_MDC
PHY2_MDIO
PHY2_RESET
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KINTEX UltraScale+ FPGA Board AXKU040 User Manual
Pin Name
_67
_67
7
67
7
67
IO_T1U_N12_67
IO_T2U_N12_67
IO_T3U_N12_67
Pin
Number
Ethernet 2 Transmit Clock
B24
B20 Ethernet 2 Transmit Data bit0
A20 Ethernet 2 Transmit Data bit1
B21 Ethernet 2 Transmit Data bit2
B22 Ethernet 2 Transmit Data bit3
Ethernet 2 Transmit Enable Signal
A24
Ethernet 2 Receive Clock
D23
Ethernet 2 Receive Data Bit0
B29
A28 Ethernet 2 Receive Data Bit1
A27 Ethernet 2 Receive Data Bit2
Ethernet 2 Receive Data Bit3
C23
Ethernet 2 Receive Data Enable Signal
A29
Ethernet 2 MDIO Management
A23
A22 Ethernet 2 MDIO Management Data
H22
Description
Clock
Ethernet Chip Reset
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