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2) PCI INTERFACE
Symbol
Type
AD31-0
T/S
120-123, 125-128, 4-
6, 8-11, 13, 26-29, 31-
C/BE3-0
T/S
CLK
I
CLKRUNB
I/O
DEVSELB
S/T/S
FRAMEB
S/T/S
GNTB
I
REQB
T/S
IDSEL
I
INTAB
O/D
IRDYB
S/T/S
TRDYB
S/T/S
PAR
T/S
PERRB
S/T/S
SERRB
O/D
STOPB
S/T/S
RSTB
I
3) FLASH/EEPROM INTERFACE
Symbol
Type
MA16-3
O
70-63, 61, 60, 57, 53-51 Boot PROM address bus: These pins are used to access up to 128k-byte flash memory or
MA8
I/O
MA6/9356SEL
I/O
MA2/EESK
O
MA1/EEDI
O
MA0/EEDO
O, I
EECS
O
Pin No
PCI address and data multiplexed pins.
34, 37-39, 41-45
2, 14, 24, 36
PCI bus command and byte enables multiplexed pins.
116
Clock provides timing for all transactions on PCI and is input to PCI device.
75
Clock Run: This signal is used by RTL8139C(L) to request starting (or speeding up) the clock,
CLK. CLKRUNB also indicates the clock status. For RTL8139C(L), CLKRUNB is an open drain
output and also an input. The RTL8139C(L) requests the central resource to start, speed up, or
maintain the interface clock by the assertion of CLKRUNB. For the host system, it is an S/T/S sig-
nal. The host system (central resource) is responsible for maintaining CLKRUNB asserted, and for
driving it high to the negated (deasserted) state.
19
Device Select: The RTL8139C(L) asserts this signal low when it recognizes its target address after
FRAMEB is asserted. As a bus master, the RTL8139C(L) samples this signal to insure that a PCI
target recognizes the destination address for the data transfer.
15
Cycle Frame is driven by the current master to indicate the beginning and duration of an access.
FRAMEB is asserted to indicate a bus transaction is beginning. While FRAMEB is asserted, data
transfers continue. When FRAMEB is deasserted, the transaction is in the final data phase.
117
Grant: This signal is asserted low to indicate to the RTL8139C(L) that the central arbiter has
granted the ownership of the bus to the RTL8139C(L).
118
Request: The RTL8139C(L) will assert this signal low to request the ownership of the bus to the
central arbiter.
3
Initialization Device Select is used as a chip-select during configuration read and write transac-
tions.
114
INTAB is used to request an interrupt.
16
Initiator Ready indicates the initiating agent's ability to complete the current data phase of the
transaction.
17
Target Ready indicates the target agent's ability to complete the current phase of the transaction.
23
Parity is even parity across AD31-0 and C/BE3-0.
21
Parity Error: When the RTL8139C(L) is the bus master and a parity error is detected, the
RTL8139C(L) asserts both SERR bit in ISR and Configuration Space command bit 8 (SERRB
enable). Next, it completes the current data burst transaction, then stops operation and resets
itself. After the host clears the system error, the RTL8139C(L) continues its operation.
When the RTL8139C(L) is the bus target and a parity error is detected, the RTL8139C(L) asserts
this PERRB pin.
22
System Error: If an address parity error is detected and Configuration Space Status register bit 15
(detected parity error) is enabled, RTL8139C(L) asserts both SERRB pin and bit 14 of Status reg-
ister in Configuration Space.
20
Stop: Indicates the current target is requesting the master to stop the current transaction.
115
Reset: When RSTB is asserted low, the RTL8139C(L) performs internal system hardware reset.
RSTB must be held for a minimum of 120 ns periods.
Pin No
EPROM.
61
Output pin as part of Boot PROM(or Flash) address bus after PCI reset.
Input pin as Aux. Power detect pin to detect if Aux. Power exists or not, when initial power-on or
PCI reset is asserted. Besides connecting this pin to Boot PROM, it should be pulled high to the
Aux. Power via a resistor to detect Aux. power. If this pin is not pulled high to Aux.
Power, the RTL8139C(L) assumes there is no Aux. power exists. To support wakeup from ACPI
D3cold or APM power-down, this pin must be pulled high to aux. power via a resistor.
57
When this pin is pulled high with a 10K [ resistor, the 93C56 EEPROM is used to store the
resource data and CIS for the RTL8139C(L). The RTL8139C(L) latches the status of this pin at
power-up to determine what EEPROM(93C46 or 93C56) is used, afterwards, this pin is used as
MA6.
49
The MA2-0 pins are switched to EESK, EEDI, EEDO in 93C46 (93C56) programming or auto-load
mode.
48
47
50
93C46 (93C56) chip select
UP-5900VS CIRCUIT DESCRIPTION
5 – 48
Description
Description
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