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Name
Type
SMEMR#
O
SMEMW#
O
ZEROWS#
I
■ ■ ■ ■ X-BUS INTERFACE
Name
Type
A20GATE
I
BIOSCS#
O
KBCCS#/
O
GPO26
MCCS#
O
PCS0#
O
PCS1#
RCIN#
I
RTCALE/
O
GPO25
RTCCS#/
O
GPO24
XDIR#/
O
GPO22
XOE#/
O
GPO23
STANDARD MEMORY READ. PIIX4E asserts SMEMR# to request an ISA memory slave to drive data onto the
data lines. If the access is below the 1-Mbyte range (00000000h 000FFFFFh) during DMA compatible, PIIX4E mas-
ter, or ISA master cycles, PIIX4E asserts SMEMR#. SMEMR# is a delayed version of MEMR#.
During Reset: High-Z
After Reset: High
STANDARD MEMORY WRITE. PIIX4E asserts SMEMW# to request an ISA memory slave to accept data from the
data lines. If the access is below the 1-Mbyte range (00000000h 000FFFFFh) during DMA compatible, PIIX4E mas-
ter, or ISA master cycles, PIIX4E asserts SMEMW#. SMEMW# is a delayed version of MEMW#.
During Reset: High-Z
After Reset: High
ZERO WAIT STATES. An ISA slave asserts ZEROWS# after its address and command signals have been decoded
to indicate that the current cycle can be shortened. A 16-bit ISA memory cycle can be reduced to two SYSCLKs. An
8-bit memory or I/O cycle can be reduced to three SYSCLKs. ZEROWS# has no effect during 16-bit I/O cycles.
If IOCHRDY is negated and ZEROWS# is asserted during the same clock, then ZEROWS# is ignored and wait
states are added as a function of IOCHRDY.
ADDRESS 20 GATE. This input from the keyboard controller is logically combined with bit 1 (FAST_A20) of the Port
92 Register, which is then output via the A20M# signal.
BIOS CHIP SELECT. This chip select is driven active during read or write accesses to enabled BIOS memory
ranges. BIOSCS# is driven combinatorially from the ISA addresses SA[16:0] and LA[23:17], except during DMA
cycles. During DMA cycles, BIOSCS# is not generated.
During Reset: High
After Reset: High
KEYBOARD CONTROLLER CHIP SELECT. KBCCS# is asserted during I/O read or write accesses to KBC loca-
tions 60h and 64h. It is driven combinatorially from the ISA addresses SA[19:0] and LA[23:17].
If the keyboard controller does not require a separate chip select, this signal can be programmed to a general pur-
pose output.
During Reset: High
After Reset: High
MICROCONTROLLER CHIP SELECT. MCCS# is asserted during I/O read or write accesses to IO locations 62h
and 66h. It is driven combinatorially from the ISA addresses SA[19:0] and LA[23:17].
During Reset: High
After Reset: High
PROGRAMMABLE CHIP SELECTS. These active low chip selects are asserted for ISA I/O cycles which are gener-
ated by PCI masters and which hit the programmable I/O ranges defined in the Power Management section. The X-
Bus buffer signals (XOE# and XDIR#) are enabled while the chip select is active. (i.e., it is assumed that the periph-
eral which is selected via this pin resides on the X-Bus.)
During Reset: High
After Reset: High
RESET CPU. This signal from the keyboard controller is used to generate an INIT signal to the CPU.
REAL TIME CLOCK ADDRESS LATCH ENABLE. RTCALE is used to latch the appropriate memory address into
the RTC. A write to port 70h with the appropriate RTC memory address that will be written to or read from causes
RTCALE to be asserted. RTCALE is asserted on falling IOW# and remains asserted for two SYSCLKs.
If the internal Real Time Clock is used, this signal can be programmed as a general purpose output.
During Reset: Low
After Reset: Low
REAL TIME CLOCK CHIP SELECT. RTCCS# is asserted during read or write I/O accesses to RTC location 71h.
RTCCS# can be tied to a pair of external OR gates to generate the real time clock read and write command signals.
If the internal Real Time Clock is used, this signal can be programmed as a general purpose output.
During Reset: High
After Reset: High
X-BUS TRANSCEIVER DIRECTION. XDIR# is tied directly to the direction control of a 74f245 that buffers the X-Bus
data, XD[7:0]. XDIR# is asserted (driven low) for all I/O read cycles regardless if the accesses is to a PIIX4E sup-
ported device. XDIR# is asserted for memory cycles only if BIOS or APIC space has been decoded. For PCI master
initiated read cycles, XDIR# is asserted from the falling edge of either IOR# or MEMR# (from MEMR# only if BIOS or
APIC space has been decoded), depending on the cycle type. For ISA master-initiated read cycles, XDIR# is
asserted from the falling edge of either IOR# or MEMR# (from MEMR# only if BIOS space has been decoded),
depending on the cycle type. When the rising edge of IOR# or MEMR# occurs, PIIX4E negates XDIR#. For DMA
read cycles from the X-Bus, XDIR# is driven low from DACKx# falling and negated from DACKx# rising. At all other
times, XDIR# is negated high.
If the X-Bus is not used, then this signal can be programmed to be a general purpose output.
During Reset: High
After Reset: High
X-BUS TRANSCEIVER OUTPUT ENABLE. XOE# is tied directly to the output enable of a 74f245 that buffers the X-
Bus data, XD[7:0], from the system data bus, SD[7:0]. XOE# is asserted anytime a PIIX4E supported X-Bus device
is decoded, and the devices decode is enabled in the X-Bus Chip Select Enable Register (BIOSCS#, KBCCS#,
RTCCS#, MCCS#) or the Device Resource B (PCCS0#) and Device Resource C (PCCS1#). XOE# is asserted from
the falling edge of the ISA commands (IOR#, IOW#, MEMR#, or MEMW#) for PCI Master and ISA master-initiated
cycles. XOE# is negated from the rising edge of the ISA command signals for PCI Master initiated cycles and the
SA[16:0] and LA[23:17] address for ISA master-initiated cycles. XOE# is not generated during any access to an X-
Bus peripheral in which its decode space has been disabled.
If an X-Bus not used, then this signal can be programmed to be a general purpose output.
During Reset: High
After Reset: High
UP-5900VS CIRCUIT DESCRIPTION
Description
During POS: High
During POS: High
Description
During POS: High
During POS: High/GPO
During POS: High
During POS: High
During POS: Low/GPO
During POS: High/GPO
During POS: High/GPO
During POS: High/GPO
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