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11. CHIPSET (SOUTH BRIDGE)
Intel's PIIX4E is used.
11-1. PIN ASSIGHMENTS
1
2
3
4
5
6
7
8
PCIR-
AD27 IDSEL AD19 FRA-
SERR# AD13
AD9
ST#
ME #
AD31
AD26 AD23
AD18 IRDY# PAR
AD12
AD8
AD30 AD25
AD22 AD17 TRDY#
C/-
AD11
C/-
BE1#
BE0#
AD28
C/-
AD20
C/-
STOP# AD14 AD10
AD6
BE3#
BE2#
AD29 AD24 AD21
AD16
DEV-
AD15
VSS
AD7
SEL#
USB-
GPO-
IRQ9-
GPO-
VCC
VCC
P1+
28
30
OUT
PIR-
USB-
GP1-
GPO-
GPO-
VCC
QD#
P0+
21
0
27
GPI-
USB
USB
GPI-
GPI-
18
P1-
PO-
19
20
OC0# OC1#
GPI-
NC
VSS
14
(USB)
KBC-
RTC-
GPI-
GPI-
VCC
CS#
CS#
16
17
(USB)
RTC-
GPI-
CLK-
PCS0#
GPI-
ALE
13
48
15
REQ-
BIOS-
XDIR# XOE#
NC
A#
CS#
GNTA# REQ-
NC
MCCS# PCS1#
B#
A20-
GNT-
REQ-
GNT-
PIR-
GATE
B#
C#
C#
QC#
CPU_-
PCI_-
PIR-
PIR-
NC
VCC
VCC
STP#
STP#
QA#
QB#
SD6
SD3
IOCH-
IOW# SA16
VCC
SYS-
SA9
RDY
CLK
IRQ9
SD2
SME-
SA18
DRE-
DRE-
SA11
IRQ5
MW#
Q3
Q1
SD7
DRE-
SD0
SA19 DACK-
SA14
SA12
IRQ6
Q2
3#
RST-
SD4
SD1
SME-
SA17 DACK-
REFR-
SA10
DRV
MR#
1#
ESH#
IOCHK# SD5 ZERO-
AEN
IOR#
SA15
SA13
IRQ7
WS#
NOTE: For multiplexed pins, only one of the two signal names is shown in this figure. For example, the name
for "Y20" only lists IRQ8#(instead of IRQ8#/GPI6). The pin list in Table 69 includes both signal names
for the multiplexed pins.
11-2. PIN DISCRIPTION
1) PIIX4E Signals
■ ■ ■ ■ PCI BUS INTERFACE
Name
Type
AD[31:0]
I/O
C/BE#[3:0]
I/O
CLKRUN#
I/O
DEVSEL#
I/O
FRAME#
I/O
9
10
11
12
13
14
15
16
17
18
AD5
AD1 PCIR-
PHLD-
SDD6 SDD4 SDD13 SDDR-
SDD-
SDA2 PDD8 PDD7
EQB#
A#
EQ
ACK#
AD4
AD0 PCIR-
PHO-
SDD9 SDD-
SDD1
SDI-
SDA1 SDC-
EQC#
LD#
11
OW#
S1#
CLK-
AD3
PCIR-
SDD7 SDD5 SDD3 SDD14
SDI-
SDA0 SDC-
RUN#
EQD#
OR#
S3#
AD2
VSS
PCI-
SDD8
SDD10
SDD2 SDD15
SIO-
PDD-
PDD3 PDD-
CLK
RDY
12
VCC
PCIR-
VCC
VCC
VSS
SDD12 SDD0
VCC PDD14 PDD1 PDD13 PDD2
EQA#
VCC
VCC
PDI-
PDI-
PDD-
OW#
OR#
REQ
PDA0 PDA2 PDA1 PDD-
PDC-
PDC-
API-
S3#
S1#
CCS#
VSS
VSS
VSS
VSS
VREF
APIC-
STP-
ACK#
CLK#
VSS
VSS
VSS
VSS
ZZ
SPKR APIC-
REQ#
VSS
VSS
VSS
VSS
VCC
IGN-
INIT
(RTC)
NE#
VSS
VSS
VSS
VSS
NC
RSM-
PWR
RST#
OK
VCC
SMBAL-
NC
(SUS)
ERT#
VCC
LID
SUS-
RI#
CLK
VCC
VCC
CON-
CON-
(SUS)
FIG1
FIG2
IRQ3
SA4
SA1
LA23
IRQ-
LA18 DACK-
SD9
SUS_
SUS_
12/M
5#
STAT1#
STAT2#
SA6
BALE
SA0
IRQ10 LA20 DACK-
MEM-
DRE-
DRE-
SUSC# BAT-
0#
W#
Q6
Q7
SA7
TC
OSC
IOCS-
LA21 IRQ14 MEM-
DACK-
SD11 TEST# SUSB# EXT-
16#
R#
6#
IRQ4
SA5
SA2
SBH-
IRQ11 LA19
DRE-
SD8 DACK-
SD13 SD15 SUSA#
E#
Q0
7#
SA8 DACK-
SA3
MEM-
LA22 IRQ15 LA17
DRE-
SD10 SD12 SD14 IRQ8#
2#
CS16#
Q5
PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction,
AD[31:0] contain a physical byte address (32 bits). During subsequent clocks, AD[31:0] contain data.
A PIIX4E Bus transaction consists of an address phase followed by one or more data phases. Little-endian byte
ordering is used. AD[7:0] define the least significant byte (LSB) and AD[31:24] the most significant byte (MSB).
When PIIX4E is a Target, AD[31:0] are inputs during the address phase of a transaction. During the following data
phase(s), PIIX4E may be asked to supply data on AD[31:0] for a PCI read, or accept data for a PCI write.
As an Initiator, PIIX4E drives a valid address on AD[31:2] and 0 on AD[1:0] during the address phase, and drives
write or latches read data on AD[31:0] during the data phase.
During Reset: High-Z
After Reset: High-Z
BUS COMMAND AND BYTE ENABLES. The command and byte enable signals are multiplexed on the same PCI
pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/
BE[3:0]# are used as Byte Enables. The Byte Enables determine which byte lanes carry meaningful data.
C/BE0# applies to byte 0, C/BE1# to byte 1, etc. PIIX4E drives C/BE[3:0]# as an Initiator and monitors C/BE[3:0]#
as a Target.
During Reset: High-Z
After Reset: High-Z
CLOCK RUN#. This signal is used to communicate to PCI peripherals that the PCI clock will be stopped. Peripher-
als can assert CLKRUN# to request that the PCI clock be restarted or to keep it from stopping. This function follows
the protocol described in the PCI Mobile Design Guide, Revision 1.0.
During Reset: Low
After Reset: Low
DEVICE SELECT. PIIX4E asserts DEVSEL# to claim a PCI transaction through positive decoding or subtractive
decoding (if enabled). As an output, PIIX4E asserts DEVSEL# when it samples IDSEL active in configuration cycles
to PIIX4E configuration registers. PIIX4E also asserts DEVSEL# when an internal PIIX4E address is decoded or
when PIIX4E subtractively or positively decodes a cycle for the ISA/EIO bus or IDE device. As an input, DEVSEL#
indicates the response to a PIIX4E initiated transaction and is also sampled when deciding whether to subtractively
decode the cycle. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated until
driven by PIIX4E as a target.
During Reset: High-Z
After Reset: High-Z
CYCLE FRAME. FRAME# is driven by the current Initiator to indicate the beginning and duration of an access.
While FRAME# is asserted data transfers continue. When FRAME# is negated the transaction is in the final data
phase. FRAME# is an input to PIIX4E when it is the Target. FRAME# is an output when PIIX4E is the initiator.
FRAME# remains tri-stated until driven by PIIX4E as an Initiator.
During Reset: High-Z
After Reset: High-Z
19
20
A
B
PDD9
PDD6
C
PDD10 PDD5
D
PDD4
11
E
F
PDD15 PDD0
G
PIO-
ACK#
RDY
H
THRM# IRQ0
J
SER-
IRQ1
IRQ
K
FERR# SLP#
L
INTR
NMI
M
CPU-
A20-
RST
M#
N
RTCX1 RCIN#
P
GPI-
SMI#
1
R
SMB-
RTC-
CLK
X2
T
GPO-
SMB-
8
DATA
U
PWR-
LOW#
BTN#
V
SMI#
W
Y
pix4_pin
Description
During POS: High-Z
During POS: High-Z
During POS: High
During POS: High-Z
During POS: High-Z
UP-5900VS CIRCUIT DESCRIPTION
5 – 18
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