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Sharp UP-5300 Service Manual

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CHAPTER 1. SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
CHAPTER 2. OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
CHAPTER 3. SERVICE PRECAUTION . . . . . . . . . . . . . . . . . . . . . 3-1
CHAPTER 4. UP-5300 DIAGNOSTICS SPECIFICATIONS . . . . . . 4-1
CHAPTER 5. CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 5-1
CHAPTER 6. BIOS SETUP UTILITY . . . . . . . . . . . . . . . . . . . . . . . . 6-1
CHAPTER 8. CIRCUIT DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
CHAPTER 9. PWB LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Parts marked with "!" is important for maintaining the safety of the set. Be sure to replace these parts with specified
ones for maintaining the safety and performance of the set.
CONTENTS
CODE: 00ZUP5300USME
POS TERMINAL
UP-5300
MODEL
("U" & "A" version)
This document has been published to be used
for after sales service only.
The contents are subject to change without notice.

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  • Page 1: Table Of Contents

    CHAPTER 3. SERVICE PRECAUTION ..... 3-1 CHAPTER 4. UP-5300 DIAGNOSTICS SPECIFICATIONS ..4-1 CHAPTER 5. CIRCUIT DESCRIPTION ..... 5-1 CHAPTER 6.
  • Page 2 BATTERY DISPOSAL Contains Nickel Metal Hydride Battery. Must be Disposed of Properly. Contact Local Environmental Officials for Disposal Instructions.

  • Page 3: Chapter 1. Specifications

    3-2. Keyboard CHAPTER 1. SPECIFICATIONS ITEM SPECIFICATIONS NOTE Type Touch key 1. Appearance (Analog touch panel) 4096 (W) × 4096 (H) Number of key positions positions Control Mouse emulation 3-3. PC system ITEM SPECIFICATIONS NOTE Pentium processor Chip set FireStar Plus: 82C700U3.2 Graphic controller VGAC : MN89305...
  • Page 4 Use this switch only when the main power source is not cut off even if the main unit power switch is set to OFF position. UP-5300 is turned OFF and the hardware is reset by turning the main power switch OFF and then pressing the shutdown switch.

  • Page 5: Sharp Corporation

    DSW-1 (Local production) SCSI Touch Panel Ethernet Function ON (value=0) POS Devlce Driver (value=1) ..etc Driver Floppy Disk Not Exit Exit Controller MS-DOS Version 6.22 3-8. Power switch BIOS Hardware Provided from SHARP Corporation Power switch : 1 – 3...

  • Page 6: Sharp Corporation

    Touch panel calibration utility program (MS-DOS) — ... These software are provided with FD from SHARP corporation. Please copy contents of FD provided from department to development PC. Install to UP-5300 by using APL Install Program from PC. 4-3. Memory map 0000000h...

  • Page 7: Chapter 2. Options

    CHAPTER 2. OPTIONS 1. System configuration Incorporated in Main Unit RS-232 Communication Connection Kitchen video monitor <supplied on site> UP-5300 AT Keyboard (For North America only) <supplied on site> max.2 (RS-232) (Standard 4 channels) Drawer <Option> Remote Printer Additional ER-03DW/ <Option>...
  • Page 8 (2 Mwords × 8 bits) (4 Mwords × 16 bits) *2 HARD DISK DRIVE (Local purchase) [Outline] UP-5300 may be connected to the Hard Disk Drive. It is necessary to satisfy the 2.5 inch Hard Disk Drive specification as follows. [Specification] 2.5 inch type Hard Disk Drive...
  • Page 9 Plain view ISA bus connector: Used to check the ER-A8RS parts side. ISA bus connector: Used to check the ER-A8RS solder side. Connected to the ISA bus connector of ISA checker. Connected to the UP-5300 ISA bus connectors. 2 – 3...
  • Page 10 • • Connection diagram Plan view and connection diagram ER-A8RS solder side 150±8 ISA relay board Signal name Pin No. Pin No. Signal name STROBE- STROBE- ISA PWB ACK- ACK- BUSY BUSY ER-A8RS parts side SLCT SLCT AUTOFD- AUTOFD- ERROR- ERROR- INIT- INIT-...
  • Page 11 7pin 8pin 9pin 4-5. RS232 modular jack loop back connector: UKOG-6729BHZZ Connected to the RS232 connector (RJ45: COM3, COM4, COM5, COM6) of the UP-5300, and used to check loop signals when execut- ing diagnostics. • Connection diagram 1pin 2pin 3pin...
  • Page 12 2. Set SW1 on the BIOS loading board to the side of pin 3. Writing BIOS ROM Program NOTE: Remove all option boards from the ISA slots before writing on the BIOS ROM. 1. Install the EP-ROM (master ROM): containing a BIOS program on the BIOS loading board: CKOG-6727RCZZ.
  • Page 13 3. Open the upper cabinet. 4. Connect the BIOS loading board to the option ROM/RAM connec- tor CN5 on the main PWB, and then close the cabinet. 5. Writing the BIOS ROM program starts by turning on the power switch on the right side. To determine the status of the LED lights on the special service PWB when a BIOS ROM program is being written, see the table on the next page.
  • Page 14 <Erase ERROR in F-ROM> LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 FUNCTION (RED) (RED) (RED) (RED) (RED) (RED) (RED) (RED) (GREEN) — — — — — — Device not ready — — — — — — VPP error —...

  • Page 15: Chapter 3. Service Precaution

    Be careful to keep the air groove away from water and oil. (1) Pull the slider to the unlock position. • Do not use SHARP objects when making input entrres. 3 – 1...
  • Page 16 6. AT Keyboard usable for UP-5300 The UP-5300 can be externally connected to a keyboard. The UP-5300’s key BIOS conforms to the PC standard, but this BIOS’s operation is not compatible for some keyboards. Some keyboards may cause operation errors due to delicate timing and conflicts.
  • Page 17 2) Touch Key Pad Test ......4-5 (1) Execute the diagnostic program by rebooting the UP-5300 from 3) Linearity Test .

  • Page 18: General

    2. System configuration All memory areas are checked in units of 64KB. The checking procedures are as follows: The system requires the UP-5300, and an AT keyboard for diagnostic i. Test data 5555H is written to all the test areas. operations.

  • Page 19: Option Ram Disk Check

    ii. The test area data is saved to the main memory. Display iii. Test data 5555H is written to all the test areas. Option RAM disk Check iv. Test data and read data are compared by each word, If it is O.K., test data AAAAH is written to the test area.

  • Page 20: Standard Flash Rom Check

    When "YES" is selected Terminating method • Move cursor to select "YES", and the message in ( ) will be After the test result is displayed, press Esc key to terminate and displayed. return to the ROM diagnostics menu. • If the verify check is made, the test area is first erased.

  • Page 21: Real Time Clock Check

    1) Real time clock Check 1) Controller Diag Test Checking content Checking content RTC timer function and RTC clock function are tested. After initializing the controller, the diagnostic command is ex- ecuted. The procedures are as follows: In RTC timer check, the RTC timer is set so that an interrupt is •...

  • Page 22: Linearity Test

    Loop cable (UKOG-6717RCZZ) wiring diagram Checking content Key code inserted to the clerk key switch which is then displayed in a decimal value. UP-5300 : PARALLEL1 OUTPUT MODE Display A8RS : PARALLEL3 INPUT MODE Clerk Key Check Clerk Key Code Opposite ER-A8RS setting The clerk code is displayed at XX.

  • Page 23: Parallel2 Loop Check

    PARALLEL1 for testing. Set the jumpers on the PWB prior to the test as shown in Fig. 3-6. Terminating method. Press the Esc key to terminate and return to the Printer diagnos- UP-5300 : PARALLEL1 OUTPUT MODE tics menu. A8RS : PARALLEL3 INPUT MODE 2) PARALLEL2 Loop Check Checking content A loop check is performed for ER-A8RS I/O address 278H ∼...

  • Page 24: Parallel2 Print Check

    Display PARALLEL1 Print Check PARALLEL1 Channel Disabled "PARALLEL1 Channel Disabled" is displayed only when no ac- cess to PARALLEL1 is allowed. Fig. 3-10 Jumper pin setting Terminating method. The test procedures are as follows: Press the Esc key to terminate and return to the Printer diagnos- i.

  • Page 25: Serial I/O Diagnostics

    Therefore, when an ER-A8RS is used, you must set COM1, 2, 5, and The loop back check is performed for the UART at I/O address 6 on the UP-5300 side, and set COM3 and 4 on the ER-A8RS side. 2F8H ∼ 2FFH. The check procedure, the display, and the ter- The following menu is displayed.

  • Page 26: Com4 Check

    iv. Reversed pattern of pattern iii. 4) COM4 Check Checking content The loop back check is performed for the UART at I/O address 2E8H ∼ 2EFH. The check procedure, the display, and the ter- minating method are the same as COM3 Check. 5) COM5 Check Checking content The loop back check is performed for the UART at I/O address...

  • Page 27: Magnetic Card Reader Diagnostics

    After reading data, the FIFO buffer is reset. Display MCR (Magnetic Card Reader) Check 1) Drawer 1 check TRACK1: SHARP TEST CARD 0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789 UKOG-6718RCZZ Checking content TRACK2: The drawer 1 solenoid is turned on and the drawer open sensor 0123456789012345678901234567 value is sensed at every 100ms and the state is displayed.

  • Page 28: Drawer 2 Check

    3-17. IDE I/F & Hard Disk Diagnostics Display The hard disk is tested and the information stored in the hard disk is displayed. Drawer 1 Check The following tests are executed. • Drawer Open Sensor : OPEN (or CLOSE) Read test: Seek (sequential, random) test, read only (target cylinder, target sector), and dump test •...

  • Page 29: Random Seek Test

    • Test Start ? [Yes/No] Display Selection is made to execute the test or not. Same as the above sequential read, however the following con- tents are different. Checking content The test Point is changed at random in the range of 000 ∼ XXX In the cylinder range set above, the sequential seek is executed (cylinder range set value).

  • Page 30: Target Sector Read Test

    (On the above screen, the thick figures are selected, and the thick Terminating method figure values are selected.) The methods to interrupt, resume, and terminate the test are On the above screen, when the pass count is counted up (when same as (2) Sequential read.

  • Page 31: Controller Check Test

    The correct password is "sharp" or "SHARP" in 5 digits. When When "1 Pass" is set, a series of tests is made only once.

  • Page 32: Target Sector Write/Read-Verify Test

    10) Target Sector Write/Read-verify Test Display [Test conditions setting] Similar to the previous 5). Cylinder range setting is 000 ↔ (Final Error Logging Area Clear cylinder 2). @Test Start ? [Yes No] At first No is highlighted. Checking content For the cylinder range, the head number, and the sector number Guidance before execution of the test : Move ESC : Exit ENTER : Select area set in the above, write/read/verify is made.

  • Page 33: Fdd Diagnostics

    Terminating testing Last cylinder When the screen displays the following message, remove the FD Head of 0 head, 1 sector 2nd sector - 6th sector are the same. and press any key. Counter [1byte 0~46] Please out W/R-TEST disk from drive Error Cylinder Head Sector...

  • Page 34: Chapter 5. Circuit Description

    1-7. Memory CHAPTER 5. CIRCUIT DESCRIPTION • L2 cache: None DRAM Standard = 1M × 16b EDO • System Memory: Asym 60ns Vcc = 3.3V × 4chip (8MB) Option = 144pin S.O.DIMM socket 1-1. CPU × 1 (8MB/16MB/32MB) Pentium Processor: A80502CSLM66133SY028 512K ×...

  • Page 35: Block Diagram

    2. Block Diagram Main PCB Power Pentium EDO DRAM Supply +12V FireStar Plus ctrl RAS/CAS 82C700U3.2 -12V 144pin 14.318MHz S.O.DIMM MK1492-04R VGA PCB 32.768kHz Dctrl 25.175MHz Buzzer VGAC Video RAM MN89305 3.3V DC-DC 32.768kHz ctrl Convetor bq3285ESS PCI Bus Dctrl Buffer 2.5"...

  • Page 36: Memory Map

    3. Memory Map Main Memory(System) 0000000 EDO DRAM Standard A0000 VGA RAM 128KB 0800000 FPM/EDO DRAM Option 8Byte SOD 1000000 FPM/EDO DRAM Option 8Byte SOD 16MB C0000 1800000 NOTE: VGA BIOS When the system installer is started, the System 32KB BIOS ROM uses addresses from C0000h to CAFFFh.
  • Page 37 4-2. POS specification 4. I/O Address Map UP-5300 4-1. PC specification Address POS I/O Address Legacy ISA I/O 180-189 Extended Interrupt control 00-0F DMA ch0-3 control Drawer control 10- 1F (System) 18B-18F Timer Counter control 20- 21 Master 8259 Interrupt control...
  • Page 38 6. IRQ 6-1. IRQ Mapping list Controller1 Controller2 Fixed ISA Power On UP-5x00 Available Device 8259 8259 Default Default Recommended IRQ0 System timer Timer Timer Timer IRQ1 Keyboard IRQ2 PIC cascade (Cascade) (Cascade) IRQ8 RTC/CMOS RTC/CMOS RTC/COMS RTC/CMOS IRQ9 — IRQx IRQx IRQx...
  • Page 39 Core Frequency External Bus Bus/Core Selection (max) Frequency (max) Ratio (Y33) (Y35) 100MHz 66MHz UP-5300 Setting Setting 1 = 10kohm Pull up (Vcc3) 0 = 0ohm Grounding MicroClock MK1492-04R Power-up Input Setting Pin # Name Internal Resistor Setting Function Mid-level Default...
  • Page 40 MicroClock MK1492-04R Clock Output Name Condition 14.3 14.318MHz for FireStar EHOST1 Early CPU Clock for FireStar HOST2 CPU Clock for Pentium HOST3 Not used (Host Output Clock) HOST4 Not used (Host Output Clock) HOST5,7 Not used (Host Output Clock) HOST6,8 Not used (Host Output Clock) 48M/14.3M Not used (48.0MHz Clock)
  • Page 41 7-3. Pin description Table 4. Quick Pin Reference Symbol Type Name and Function A20M# When the address bit 20 mask pin is asserted, the Pentium processor emulates the address wrap around at 1 Mbyte which occurs on the 8086. When A20M# is asserted, the processor masks physical address bit 20 (A20) before performing a lookup to the internal caches or driving a memory cycle on the bus.
  • Page 42 Symbol Type Name and Function FLUSH# When asserted, the cache flush input forces the processor to write back all modified lines in the data cache and invalidate its internal caches. A Flush Acknowledge special cycle will be generated by the processor indicating completion of the writeback and invalidation.
  • Page 43 Symbol Type Name and Function PRDY The probe ready output pin indicates that the processor has stopped normal execution in response to the R/S# pin going active or Probe Mode being entered. The page write-through pin reflects the state of the PWT bit in CR3, the page directory entry, or the page table entry. The PWT pin is used to provide and extemal writeback indication on a page-by-page basis.
  • Page 44 8-2. Pin assignments HD48 HD49 HD50 HD52 HD55 HD59 SDCKE* TAG4 TAG- CAS3# CAS7# MD61 MD56 MD52 MD47 MD42 MD38 MD33 MD29 MD25 MD22 MD20 CAS# H46D HD47 HD51 HD53 HD56 HD60 RSVD TAG7 TAG3 CAS0# CAS4# RAS2# MA10 MD60 MD55 MD51 MD46...
  • Page 45 8-3. Pin description 8-3-1. CPU Interface Signals Set Signal Type Signal Name Pin No. Selected By Signal Description (Drive) Host Data Bus HD[63:0] Refer to Host Data Bus Lines 63 through 0: Provides a 64-bit data path to Table 3-2 (4mA) the CPU.
  • Page 46 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) Next Address: This signal is connected to the CPU’s NA# pin to (4mA) request pipelined addressing for local memory cycle. FireStar asserts NA# for one clock when the system is ready to accept a new address from the CPU, even if all data transfers for the current cycle have not completed.
  • Page 47 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) TAG3 SYSCFG Tag RAM Data Bit3: This input signal becomes an output whenever (4mA) 00h[5] = 0 TAGWE# is activated to write a new tag to the Tag RAM. 11h[3] = 0 TAG4 SYSCFG...
  • Page 48 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) SDRAS# SDAM Row Address Strobe (primary copy): This output is part of the SDRAM command combination. This pin should be connected to the SDRAM through a damping resistor. DWE# Cycle DRAM Write Enable (primary copy): This signal is the common (8mA)
  • Page 49 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) SERR# AD17 System Error: SERR# can be pulsed active by any PCI device that (PCI) detects a system error condition. Upon sampling SERR# active, FireStar generates a non-maskable interrupt (NMI) to the 3.3V Pentium CPU.
  • Page 50 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) OSC32 32KHz Clock: This signal is used as a 32KHz clock input. It is used for power management and is usually the only active clock when the system is in Suspend mode. OSC32 is a 5.0V tolerant input, even when its power plane is connected to 3.3.V as long as the 5VREF pins of FireStar are connected to +5.0V.
  • Page 51 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) ISA DMA Arbiter Interface DRQA/DRQ0 PCIDV1 Programmable DMA Request A/DRQ0: The DRQ is used to 99h = 00h request DMA service from the DMA controller. This input defaults to DRQ0, however, it can be programmed to route onto any internal DRQ by programming PCIDV1 C0h[2:0].
  • Page 52 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) PIO14 AC20 PCIDV1 Programmable Input/Output 14: See Section 3.3, "Programmable 8Eh ≠ 00h (4mA) I/O Pins", on page 33 for more details. CMD# AB20 SYSCFG Command: Dedicated CISA output used to signal a data transfer (4mA) 16h[7, 5] command.
  • Page 53 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) RFSH# PCIDV1 Refresh: As an output, this signal is used to inform FireStar to C2h[0] = 0 refresh the local DRAM. During normal operation, a low pulse is generated every 15µs to indicate to FireStar that the DRAM is to be refreshed if PCIDV1 64h[0] = 0.
  • Page 54 Signal Type Signal Name Pin No. Selected By Signal Description (Drive) Miscellaneous A20M# Address Bit 20 Mask: This pin is an output and generates the (4mA) A20M# output by trapping GATEA20 commands to the keyboard or to Port 092h. The CPUINIT signal to the CPU is generated whenever it senses reset commands to Port 060h/064h, or a Port 092h write command with bit 0 set high.
  • Page 55 9-2. Pin assignments The keyboard and mouse are controlled using Mitsubishi Electric’s M38802M270. No PS/2 type mouse can be used for UP-5300 because IRQ12 is not connected. In addition, A20M# of M38802M2 is not used because Firestar’s A20M# is used.

  • Page 56: Video Subsystem

    LCD. Panel Type Selection UP-5300 connects a PCI bus as the interface, and uses 2 chips of LCD Color Dual Scan UP-5300 Setting EDO DRAM configured in 256K × 16 as graphic memory so that the total capacity is 1M bytes.
  • Page 57 10-2. Pin assignments MINTEST MD10 C/BE3# MD11 C/BE2# MD12 C/BE1# MD13 C/BE0# MD14 MD15 FRAME# MD16 IDSEL MD17 BIOSCS# MD18 TEST2 MD19 TEST1 MD20 TEST0 MN89305 MD21 IRDY# MD22 AD31 MD23 AD30 MD24 AD29 MD25 TOP VIEW AD28 MD26 AD27 MD27 AD26 MD28...
  • Page 58 10-3. Pin description 10-3-1. PCI bus-related pins Pin name Level Function 5VTTL PCI Clock PCI bus synchronization clock. Possible to input up to 33MHz. AD[31:0] 5VTTL Address Data Bus Time shared PCI bus address or data bus C/BE[3:0]# 5VTTL Command/Byte Enable In the address phase, it represents memory access, I/O access, configuration access and read/write command.
  • Page 59 Pin name Level Function LCDON COMS LCD Driving Power Supply On This output is the signal which requests turning-on of the power supply for driving the LCD panel on. LOW: HIGH: On This terminal can also be used as a general-purpose I/O port. In the external RAMDAC mode, this terminal outputs the register address Bit0 to RAMDAC.
  • Page 60 10-3-5. Power Supply 11. Super I/O Pin name Level Function 11-1. Introduction Digital system power supply The FDC, serial port COM1 and COM2, and parallel port LPT1 are terminal (3.3V system) controlled by ALi’s M5113A2. Digital system power supply M5113 Hardware Setting Configuration terminal (GND) PLL VDD PLL analog system power supply...
  • Page 61 11-3. Pin description A low represents a logic 0 (0V nominal) and a high represents a logic 1 (+2.4V nominal). Name Number Type Description HOST Processor Interface D0-D7 48-51, 53-56 I/O24 Data bus. This connection is used by the host microprocessor to transmit data to and from the M5113. These pins are in a high impedance state when not in the output mode.
  • Page 62 Name Number Type Description WRTPRTJ Write Protected. This active-low Schmitt Trigger input senses from the disk drive that a disk is write- protected. Any write command is ignored. TRK0J Track 00. This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the outermost track.
  • Page 63 Name Number Type Description DRV2 Drive 2. In PS/2 mode, this input indicates whether a second drive is connected: this signal should be low if a second drive is connected. This status is reflected in a read of Status Register A. ADRxJ Optional I/O port address decode output.
  • Page 64 Type Descriptions: Input TTL compatible Input with Schmitt Trigger Input/Output with 16 mA sink @ 0.4 V, source 16 mA @ 2.4 V I/O20 I/O24 Input/Output with 24 mA sink @ 0.4 V, source 12mA @ 2.4 V Input/Output with 36 mA sink @ 0.4 V, source 8 mA @ 2.4 V I/O36 ICLK CLK input at 24 MHz...
  • Page 65 135ns from the PSC2 to OE#/RFSH# of the pseudo SRAM. So the pseudo SRAM can be refreshed automatically without Sharp’s LZ9A10000 is used as the PSC2, controlling the devices taking the arbitration with other bus masters into consideration.
  • Page 66 The PSC2 internal interrupt expansion consists of a maskable inter- SCKF is outputted to SCK pin without the logic changed and preset to rupt source register (ISR), which is the source of interface OR-com- "1" by RESET. The serial data is in the form of LSB first. SCKF posed from each interrupt input, interrupt mask register (IMR) control- operates with synchronized with SCK, and the operation speed ling the mask control , status read level register (SRL) reading the...
  • Page 67 2) After a card is scanned, the MCR interface changes serial data of 5) This MCR interface does not read the next card until interrupts are the MCR to parallel data. Changed data is written in the FIFO reset by the main CPU. buffer at every character in order from the start mark to the LRC.
  • Page 68 12-5. Pin description Signal name Function Signal name Function RTS2# RS-232 COM4/6 RTS CTS2# RS-232 COM4/6 CTS DCD2# RS-232 COM4/6 DCD Y737I SERAMIC RESONATOR CLOCK INPUT RI2# RS-232 COM4/6 RI Y737O SERAMIC RESONATOR CLOCK TXD1 RS-232 COM3/5 TXD OUTPUT RXD1 RS-232 COM3/5 RXD DTR1# RS-232 COM3/5 DTR...
  • Page 69 Signal name Function Signal name Function MEMW# ISA MEMORY WRITE COMMAND SA23 ISA BUS SA23 from CPU IOR# ISA I/O READ COMMAND from CPU PIRQ3 INTERRUPT REQUEST 3 to CPU IOW# ISA I/O WRITE COMMAND from CPU PIRQ4 INTERRUPT REQUEST 4 to CPU MCS16# MEMORY CHIP SELECT 16 to CPU PIRQ9...
  • Page 70 Bank 1 decode mode COM4 COM6 DSW-7 15. BIOS ROM Function ON (value=0) 15-1. Outline (value=1) Sharp’s LH28F004SUT-NC80 COM3 & COM3 = COM3 = COM4 IRQ IRQ11 IRQ4 Composed of erase blocks divided into 16KB even blocks assign COM4 =...
  • Page 71 17-2. Bank Base Address 20. Reset circuit The ROM disk area to be accessed is determined by inputting ad- 20-1. Block diagram dress signals from the ISA bus. The ROM disk area is base address + (0000h-3FFFh) with the size of PSC2 16KB.
  • Page 72 20-4. Shutdown Control The time in which the drawer is driven by the PSC2 is 45ms. The power switch of UP-5300 is used to switch the ON state and Time elapsed since the drawer is driven by the PSC2 until DS signal stand-by state of terminal.
  • Page 73 IATA (JIS 1 type first track): 79 characters maximum (7 bits a (2) COM3/5 character) RJ45 2 FIFOs are prepared independently to 2 channels of interface. Pin No. Signal Function These FIFOs can be read simultaneously when connected to a Request to Send MCR supporting JBA/ABA or IATA/ABA.

  • Page 74: Chapter 6. Bios Setup Utility

    Procedure for starting setup is as follows. 1 Start the system. In the Up-5300, there is an utility that rewrites minimum required setup information at the system bootup which resides in ROM-BIOS. 2 Press the following keys according to the type setup desired while Setup data is undefined at the first system startup, so setup must be SETUP Available message appears on screen.
  • Page 75 Missing or Invalid NV R/W error occured in CMOS RAM Copyright 1985-1998 Phoenix Technologies Ltd., All Rights Reserved RAM token SHARP POS Terminal Firmware Version 1.0A • Message displayed by parity error from bus (position undefined) 0000640K System RAM Passed...

  • Page 76: Chapter 7. About Utility Software And Others

    To adjust it, use the touch pen of K-PDA (Keyboard enhanced Per- Two types of UP-5300’s utility software are provided by Sharp: one is sonal Digital Assistant). used on UP-5300, and the other one is used on a PC (personal PARTS CODE PARTS NAME MODEL computer).
  • Page 77 C H A P T E R 8 . C I R C U I T D I A G R A M ( 1 / 6 ) ( 1 / 2 0 ) 1 . M A I N P W B 1 - 1 .
  • Page 78 ( 2 / 6 ) ( 2 / 2 0 ) 1 - 1 - 2 . C H I P S E T A T C o r e L o g i c F i r e S t a r ( 8 2 C 7 0 0 ) 4 3 2 - P i n B G A 8 –...
  • Page 79 1 - 1 - 3 . S Y S T E M M E M O R Y ( 3 / 6 ) ( 3 / 2 0 ) 8 – 5 8 – 6...
  • Page 80 1 - 1 - 4 . K B C & I D E I / F ( 4 / 6 ) ( 4 / 2 0 ) 8 – 7 8 – 8...
  • Page 81 1 - 1 - 5 . V G A C O N N E C T O R ( 5 / 6 ) ( 5 / 2 0 ) 8 – 9 8 – 10...
  • Page 82 8 – 11...
  • Page 83 1 - 2 . I S A S T A N D A R D ( 1 / 4 - 4 / 4 ) ( 7 / 2 0 - 1 0 / 2 0 ) ( 1 / 4 ) ( 7 / 2 0 ) 1 - 2 - 1 .
  • Page 84 8 – 14...
  • Page 85 1 - 2 - 3 . S E R I A L 1 & 2 ( 3 / 4 ) ( 9 / 2 0 ) P V C C 5 P F 1 C 1 3 1 3 3 0 p m i n i S M D 0 2 0 - 2 F B 1 0 5 B L M 3 1...
  • Page 86 1 - 2 - 4 . S L O T ( 4 / 4 ) ( 1 0 / 2 0 ) I C 3 0 C I C 3 0 D V C C 3 7 4 L S 1 2 5 7 4 L S 1 2 5 V C C 3 R 1 7 2...
  • Page 87 1 - 3 . P O S D E V I C E ( 1 / 9 - 9 / 9 ) ( 1 1 / 2 0 - 1 9 / 2 0 ) ( 1 / 9 ) ( 1 1 / 2 0 ) R X D 7 1 - 3 - 1 .
  • Page 88 1 - 3 - 2 . B I O S / D O S / R O M D I S K ( 2 / 9 ) ( 1 2 / 2 0 ) B A [ 0 . . 6 ] S A [ 0 .
  • Page 89 ( 3 / 9 ) ( 1 3 / 2 0 ) 1 - 3 - 3 . R A M D I S K S A [ 0 . . 1 7 ] S A [ 0 . . 1 7 ] S D [ 0 .
  • Page 90 8 – 25...
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  • Page 97 2 . V G A P W B ( 1 / 1 ) V C C 3 V C C 3 R 4 0 7 1 0 k M A D 5 M A D 4 M A D 3 D A 5 1 0 K 1 0 K...
  • Page 98 3 . R I S E R P W B ( 1 / 1 ) - 1 2 V 2 2 u F / 3 5 V V C C C N 3 C 1 0 2 C 1 0 3 C 1 0 4 C 1 0 5 C 1 0 6...
  • Page 99 4 . T O U C H P A N E L C O N T R O L P W B ( 1 / 1 ) & S W I T C H P W B ( 1 / 1 ) T O U C H P A N E L C O N T R O L P W B V I N A V C C...
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  • Page 102: Chapter 9. Pwb Layout

    C H A P T E R 9 . P W B L A Y O U T 1 . M a i n P W B ( F o r c o m p o n e n t s p r o d u c e d i n J a n u a r y 1 9 9 9 ) [ A S i d e ] 9 –...
  • Page 103 [ B S i d e ] 9 – 2...
  • Page 104 2 . M a i n P W B ( F o r c o m p o n e n t s p r o d u c e d i n F e b r u a r y 1 9 9 9 a n d o n w a r d ) [ A S i d e ] 9 –...
  • Page 105 [ B S i d e ] 9 – 4...
  • Page 106 3 . V G A P W B [ A S i d e ] [ B S i d e ] 9 – 5...
  • Page 107 4 . R i s e r P W B [ A S i d e ] [ B S i d e ] 5 . T / P S w i t c h P W B S w i t c h P W B 9 –...
  • Page 108 6 . I N V E R T E R P W B [ A S i d e ] [ B S i d e ] 7 . L C D R E L A Y P W B [ A S i d e ] [ B S i d e ] 9 –...

  • Page 109: Parts Guide

    UP-5300U UP-5300U PARTS GUIDE UP-5300 MODEL (for U.S.A.) CONTENTS Top cabinet etc. Bottom cabinet etc. Packing material & Accessories Main PWB unit VGA PWB unit Touch panel PWB unit Inverter PWB unit Riser PWB unit SW PWB unit LCD PWB unit Service options &...
  • Page 110 UP -5300U UP-5300U 1 Top cabinet etc. PRICE PART PARTS CODE DESCRIPTION RANK MARK RANK 1 G S T N - 2 0 0 5 B H Z Z Tilt stand 2 J K N B Z 2 4 1 1 B H Z Z Tilt konb 3 M S P R P 2 3 7 2 B H Z Z Tilt spring...
  • Page 111 UP -5300U UP -5300U 1 Top cabinet etc. PSP00124 – 2 –...
  • Page 112 UP -5300U UP-5300U 2 Bottom cabinet etc. PRICE PART PARTS CODE DESCRIPTION RANK MARK RANK 1 L X - B Z 6 7 8 2 B H Z Z Screw (3×6) 2 X E B S D 3 0 P 0 8 0 0 0 Screw (3×8) 3 L A N G K 2 8 3 9 B H Z Z Option angle 3...
  • Page 113 UP -5300U UP -5300U 2 Bottom cabinet etc. 18 20 PSP00125 – 4 –...
  • Page 114 UP -5300U UP-5300U 3 Packing material & Accessories PRICE PART PARTS CODE DESCRIPTION RANK MARK RANK 1 S P A K C 3 0 7 1 B H Z Z Packing case 2 S P A K A 8 4 5 4 B H Z Z Packing add R 3 S S A K H 0 0 0 3 D H Z Z Vinyl bag (640×560mm)
  • Page 115 UP -5300U UP -5300U 4 Main PWB unit PRICE PART PARTS CODE DESCRIPTION RANK MARK RANK Block resistor (10KΩ×4 1/32W ±5%) R M P T Q 4 1 0 3 Q C J J [BR1,5,6,7,8,10,11,13,14] Block resistor (10KΩ×4 1/32W ±5%) R M P T Q 4 1 0 3 Q C J J [BR16,17,18,19,22,23,25,29] Block resistor (10KΩ×4 1/32W ±5%)
  • Page 116 UP -5300U UP-5300U 4 Main PWB unit PRICE PART PARTS CODE DESCRIPTION RANK MARK RANK 75 Q C N C M 2 8 0 6 R C 8 J Connector (80pin)(53489-0809) [CN11] 76 Q C N C W 2 6 1 2 R C D D Connector (SO DIMM 72P*2) [CN5] 77 Q S O C Z 2 0 3 6 H C Z Z...
  • Page 117 UP -5300U UP -5300U 4 Main PWB unit PRICE PART PARTS CODE DESCRIPTION RANK MARK RANK 129 R C - E Z 1 0 6 A R C 1 A Capacitor (10µF/10V) [C7,17] 130 R C - E Z 2 2 7 1 R C 1 A Capacitor (6.3WV 220µF) [C9] 131 R C - E Z 1 0 7 2 R C 1 A...
  • Page 118 UP -5300U UP-5300U 6 Touch panel PWB unit PRICE PART PARTS CODE DESCRIPTION RANK MARK RANK 9 R C I L Z 5 0 1 7 S C Z Z Chip coil (BLM31) [FB1,3,5] 10 R C R M Z 7 0 0 2 R C Z Z Crystal (8 MHz) [X1] 11 V C C C T V 1 H H 3 3 1 J...
  • Page 119 UP -5300U UP -5300U 9 SW PWB unit PRICE PART PARTS CODE DESCRIPTION RANK MARK RANK 1 Q C N C W 1 2 7 5 A C 0 F Connector (TCS7567-01-401) [CN202] 2 Q C N C W 2 8 1 1 B H 1 F Connector (52030-1610) [CN201] 3 Q S W - Z 6 9 0 9 B H Z Z...
  • Page 120 UP -5300U UP-5300U Index PRICE PART PARTS CODE RANK MARK RANK PGUMM6731BHZZ 1- 28 PRICE PART PARTS CODE RANK MARK RANK PGUMM6732BHZZ 1- 30 PGUMM6733BHZZ 1- 29 CKOG-6727BHZZ PGUMM6734BHZZ 11-105 1- 32 CPWBN2789BH02 1- 21 PRDAF2350BHZZ 2- 18 " 10-901 PSHEG2859BHZZ 1- 38 CPWBN2794BH01...
  • Page 121 UP -5300U UP -5300U PRICE PART PRICE PART PARTS CODE PARTS CODE RANK MARK RANK RANK MARK RANK RCILF0050FCZZ VCKYTV1CB334K 4-134 4- 88 RCILZ1051LCZZ 6- 29 VCKYTV1CF105Z 4- 87 RCILZ5017SCZZ " 4- 24 " " 4- 93 7- 11 " VCKYTV1HB102K 4- 19 "...
  • Page 122 UP -5300U UP-5300U PRICE PART PRICE PART PARTS CODE PARTS CODE RANK MARK RANK RANK MARK RANK VRS-TS2AD133F VRS-TS2AD144F 4- 69 VRS-TS2AD152J 4-109 VRS-TS2AD154F 4- 68 VRS-TS2AD183J 5- 23 VRS-TS2AD203J 6- 23 VRS-TS2AD220J 4- 60 " 4-101 VRS-TS2AD222J 7- 16 VRS-TS2AD223J 4-111 VRS-TS2AD224J...
  • Page 123 © COPYRIGHT 1999 BY SHARP CORPORATION All rights reserved. Printed in Japan. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without prior written permission of the publisher.

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