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Name
Type
IDSEL
I
IRDY#
I/O
PAR
O
PCIRST#
O
PHOLD#
O
PHLDA#
I
SERR#
I/O
STOP#
I/O
TRDY#
I/O
Note:
All of the signals in the host interface are described in the Pentium Processor data sheet. The preceding table highlights PIIX4E specific uses of these
signals.
■ ■ ■ ■ ISA BUS INTERFACE
Name
Type
AEN
O
BALE
O
IOCHK#/
I
GPI0
INITIALIZATION DEVICE SELECT. IDSEL is used as a chip select during PCI configuration read and write cycles.
PIIX4E samples IDSEL during the address phase of a transaction. If IDSEL is sampled active, and the bus com-
mand is a configuration read or write, PIIX4E responds by asserting DEVSEL# on the next cycle.
INITIATOR READY. IRDY# indicates PIIX4Efs ability, as an Initiator, to complete the current data phase of the
transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY#
are sampled asserted.
During a write, IRDY# indicates PIIX4E has valid data present on AD[31:0]. During a read, it indicates PIIX4E is pre-
pared to latch data. IRDY# is an input to PIIX4E when PIIX4E is the Target and an output when PIIX4E is an Initia-
tor. IRDY# remains tristated until driven by PIIX4E as a master.
During Reset: High-Z
After Reset: High-Z
CALCULATED PARITY SIGNAL. PAR is gevenh parity and is calculated on 36 bits; AD[31:0] plus C/BE[3:0]#.
"Even" parity means that the number of "1"s within the 36 bits plus PAR are counted and the sum is always even.
PAR is always calculated on 36 bits regardless of the valid byte enables. PAR is generated for address and data
phases and is only guaranteed to be valid one PCI clock after the corresponding address or data phase. PAR is
driven and tri-stated identically to the AD[31:0] lines except that PAR is delayed by exactly one PCI clock. PAR is an
output during the address phase (delayed one clock) for all PIIX4E initiated transactions. It is also an output during
the data phase (delayed one clock) when PIIX4E is the Initiator of a PCI write transaction, and when it is the Target
of a read transaction.
During Reset: High-Z
After Reset: High-Z
PCI RESET. PIIX4E asserts PCIRST# to reset devices that reside on the PCI bus.
PIIX4E asserts PCIRST# during power-up and when a hard reset sequence is initiated through the RC register.
PCIRST# is driven inactive a minimum of 1 ms after PWROK is driven active. PCIRST# is driven for a minimum of 1
ms when initiated through the RC register. PCIRST# is driven asynchronously relative to PCICLK.
During Reset: Low
After Reset: High
PCI HOLD. An active low assertion indicates that PIIX4E desires use of the PCI Bus.
Once the PCI arbiter has asserted PHLDA# to PIIX4E, it may not negate it until PHOLD# is negated by PIIX4E.
PIIX4E implements the passive release mechanism by toggling PHOLD# inactive for one PCICLK.
During Reset: High-Z
After Reset: High
PCI HOLD ACKNOWLEDGE. An active low assertion indicates that PIIX4E has been granted use of the PCI Bus.
Once PHLDA# is asserted, it cannot be negated unless PHOLD# is negated first.
SYSTEM ERROR. SERR# can be pulsed active by any PCI device that detects a system error condition. Upon
sampling SERR# active, PIIX4E can be programmed to generate a non-maskable interrupt (NMI) to the CPU.
During Reset: High-Z
After Reset: High-Z
STOP. STOP# indicates that PIIX4E, as a Target, is requesting an initiator to stop the current transaction. As an Ini-
tiator, STOP# causes PIIX4E to stop the current transaction. STOP# is an output when PIIX4E is a Target and an
input when PIIX4E is an Initiator. STOP# is tri-stated from the leading edge of PCIRST#. STOP# remains tri-stated
until driven by PIIX4E as a slave.
During Reset: High-Z
After Reset: High-Z
TARGET READY. TRDY# indicates PIIX4Efs ability to complete the current data phase of the transaction. TRDY#
is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted.
During a read, TRDY# indicates that PIIX4E, as a Target, has place valid data on AD[31:0]. During a write, it indi-
cates PIIX4E, as a Target is prepared to latch data. TRDY# is an input to PIIX4E when PIIX4E is the Initiator and an
output when PIIX4E is a Target.
TRDY# is tri-stated from the leading edge of PCIRST#. TRDY# remains tri-stated until driven by PIIX4E as a slave.
During Reset: High-Z
After Reset: High-Z
ADDRESS ENABLE. AEN is asserted during DMA cycles to prevent I/O slaves from misinterpreting DMA cycles as
valid I/O cycles. When negated, AEN indicates that an I/O slave may respond to address and I/O commands. When
asserted, AEN informs I/O resources on the ISA bus that a DMA transfer is occurring. This signal is also driven high
during PIIX4E initiated refresh cycles.
During Reset: High-Z
After Reset: Low
BUS ADDRESS LATCH ENABLE. BALE is asserted by PIIX4E to indicate that the address (SA[19:0], LA[23:17])
and SBHE# signal lines are valid. The LA[23:17] address lines are latched on the trailing edge of BALE. BALE
remains asserted throughout DMA and ISA master cycles.
During Reset: High-Z
After Reset: Low
I/O CHANNEL CHECK. IOCHK# can be driven by any resource on the ISA bus. When asserted, it indicates that a
parity or an uncorrectable error has occurred for a device or memory on the ISA bus. A NMI will be generated to the
CPU if the NMI generation is enabled. If the EIO bus is used, this signal becomes a general purpose input.
UP-5900VS CIRCUIT DESCRIPTION
Description
During POS: High-Z
During POS: High-Z
During POS: High
During POS: High
During POS: High-Z
During POS: High-Z
During POS: High-Z
Description
During POS: Low
During POS: Low
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