Advertisement
Name
Type
GCKE/CKE1
O
CMOS
SRAS[B,A]#
O
CMOS
CKE0/FENA
O
CMOS
SCAS[B,A]#
O
CMOS
MAA[13:0]
O
MAB[12:11]#
CMOS
MAB[13,10]
MAB[9:0]#
WEA#
O
WEB#
CMOS
MD [63:0]
I/O
CMOS
MECC[7:0]
I/O
CMOS
3) PCI Interface (Primary)
■ ■ ■ ■ Primary PCI Interface Signals
Name
Type
AD[31:0]
I/O
PCI
DEVSEL#
I/O
PCI
FRAME#
I/O
PCI
IRDY#
I/O
PCI
C/BE[3:0]#
I/O
PCI
Global CKE (SDRAM): Global CKE is used in a 4 DIMM configuration requiring power down mode for the SDRAM.
External logic must be used to implement this function.
SDRAM Clock Enable (CKE1): In mobile mode, SDRAM Clock Enable is used to signal a self-refresh or power-down
command to an SDRAM array when entering system suspend. CKE is also used to dynamically power down inactive
SDRAM rows. The combination of SDRAMPWR (SDRAM register) and MMCONFIG (DRAMC register) determine the
functioning of the CKE signals. Refer to the DRAMC register for more details.
SDRAM Row Address Strobe (SDRAM): The SRAS[B,A]# signals are multiple copies of the same logical SRASx sig-
nal (for loading purposes) used to generate SDRAM command encoded on SRASx/SCASx/WE signals.
SDRAM Clock Enable 0 (CKE0). In mobile mode, CKE0 SDRAM Clock Enable is used to signal a self-refresh or
power-down command to an SDRAM array when entering system suspend. CKE is also used to dynamically power
down inactive SDRAM rows.
FET Enable (FENA): In a 4 DIMM configuration. FENA is used to select the proper MD path through the FET switches.
SDRAM Column Address Strobe (SDRAM): The SCAS[B,A]# signals are multiple copies of the same logical SCASx
signal (for loading purposes) used to generate SDRAM command encoded on SRASx/SCASx/WE signals.
Memory Address(EDO/SDRAM): MAA[13:0] and MAB[13:0]# are used to provide the multiplexed row and column
address to DRAM. There are two sets of MA signals which drive a max. of 2 DIMMs each. MAA[12:11,9:0] are inverted
copies of MAB[12:11,9:0]#. MAA[13,10] and MAB[13,10] are identical copies.
Each MAA/MAB[13:0] line has a programmable buffer strength to optimize for different signal loading conditions.
Write Enable Signal (EDO/SDRAM): WE# is asserted during writes to DRAM.
The WE# lines have a programmable buffer strength to optimize for different signal loading conditions.
Memory Data (EDO/SDRAM): These signals are used to interface to the DRAM data bus.
Memory ECC Data (EDO/SDRAM): These signals carry Memory ECC data during access to DRAM.
PCI Address/Data: These signals are connected to the PCI address/data bus.
Address is driven by the 82443BX with FRAME# assertion, data is driven or received in the following clocks. When the
82443BX acts as a target on the PCI Bus, the AD[31:0] signals are inputs and contain the address during the first clock
of FRAME# assertion and input data (writes) or output data (reads) on subsequent clocks.
Device Select: Device select, when asserted, indicates that a PCI target device has decoded its address as the target
of the current access. The 82443BX asserts DEVSEL# based on the DRAM address range or AGP address range
being accessed by a PCI initiator. As an input it indicates whether any device on the bus has been selected.
Frame: FRAME# is an output when the 82443BX acts as an initiator on the PCI Bus.
FRAME# is asserted by the 82443BX to indicate the beginning and duration of an access. The 82443BX asserts
FRAME# to indicate a bus transaction is beginning.
While FRAME# is asserted, data transfers continue. When FRAME# is negated, the transaction is in the final data
phase. FRAME# is an input when the 82443BX acts as a PCI target. As a PCI target, the 82443BX latches the C/
BE[3:0]# and the AD[31:0] signals on the first clock edge on which it samples FRAME# active.
Initiator Ready: IRDY# is an output when 82443BX acts as a PCI initiator and an input when the 82443BX acts as a
PCI target. The assertion of IRDY# indicates the current PCI Bus initiator's ability to complete the current data phase of
the transaction.
Command/Byte Enable: PCI Bus Command and Byte Enable signals are multiplexed on the same pins. During the
address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are used as
byte enables. The byte enables determine which byte lanes carry meaningful data. PCI Bus command encoding and
types are listed below.
C/BE[3:0]# Command Type
0000 Interrupt Acknowledge
0001 Special Cycle
0010 I/O Read
0011 I/O Write
0100 Reserved
0101 Reserved
0110 Memory Read
0111 Memory Write
1000 Reserved
1001 Reserved
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
1101 Reserved (Dual Address Cycle)
1110 Memory Read Line
1111 Memory Write and Invalidate
Description
Description
UP-5900VS CIRCUIT DESCRIPTION
5 – 14
Advertisement
Chapters
