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Name
Type
PDDREQ
I
PDIOR#
O
PDIOW#
O
PIORDY
I
SDA[2:0]
O
SDCS1#
O
SDCS3#
O
SDD[15:0]
I/O
PRIMARY DISK DMA REQUEST. This input signal is directly driven from the IDE device DMARQ signal. It is
asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function.
It is not associated with any AT compatible DMA channel.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
PRIMARY DISK IO READ. In normal IDE this is the command to the IDE device that it may drive data onto the
PDD[15:0] lines. Data is latched by PIIX4E on the negation edge of PDIOR#. The IDE device is selected either by
the ATA register file chip selects (PDCS1#, PDCS3#) and the PDA[2:0] lines, or the IDE DMA slave arbitration sig-
nals (PDDACK#).
In an Ultra DMA/33 read cycle, this signal is used as DMARDY# which is negated by the PIIX4E to pause Ultra
DMA/33 transfers. In an Ultra DMA/33 write cycle, this signal is used as the STROBE signal, with the drive latching
data on rising and falling edges of STROBE.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High
After Reset: High
PRIMARY DISK IO WRITE. In normal IDE mode, this is the command to the IDE device that it may latch data from
the PDD[15:0] lines. Data is latched by the IDE device on the negation edge of PDIOW#. The IDE device is selected
either by the ATA register file chip selects (PDCS1#, PDCS3#) and the PDA[2:0] lines, or the IDE DMA slave arbi-
tration signals (PDDACK#).
For Ultra DMA/33 mode, this signal is used as the STOP signal, which is used to terminate an Ultra DMA/33 trans-
action. If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding
signal on the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High
After Reset: High
PRIMARY IO CHANNEL READY. In normal IDE mode, this input signal is directly driven by the corresponding IDE
device IORDY signal.
In an Ultra DMA/33 read cycle, this signal is used as STROBE, with the PIIX4E latching data on rising and falling
edges of STROBE. In an Ultra DMA/33 write cycle, this signal is used as the DMARDY# signal which is negated by
the drive to pause Ultra DMA/33 transfers.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
This is a Schmitt triggered input.
SECONDARY DISK ADDRESS[2:0]. These signals indicate which byte in either the ATA command block or control
block is being addressed. If the IDE signals are configured for Primary and Secondary, these signals are connected
to the corresponding signals on the Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High-Z
After Reset: Undefined
SECONDARY CHIP SELECT FOR 170H-177H RANGE. For ATA command register block. If the IDE signals are
configured for Primary and Secondary, this output signal is connected to the corresponding signal on the Secondary
IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High
After Reset: High
SECONDARY CHIP SELECT FOR 370H-377H RANGE. For ATA control register block. If the IDE signals are con-
figured for Primary and Secondary, this output signal is connected to the corresponding signal on the Secondary
IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High
After Reset: High
SECONDARY DISK DATA[15:0]. These signals are used to transfer data to or from the IDE device. If the IDE sig-
nals are configured for Primary and Secondary, these signals are connected to the corresponding signals on the
Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High-Z
After Reset: Undefined
UP-5900VS CIRCUIT DESCRIPTION
Description
During POS: High
During POS: High-Z
1
During POS: SDA
During POS: High
During POS: High-Z
1
During POS: SDD
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