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Name
Type
HITM#
I/O
GTL+
HLOCK#
I
GTL+
HREQ[4:0]#
I/O
GTL+
HTRDY#
I/O
GTL+
RS[2:0]#
I/O
GTL+
Note:
1. All of the signals in the host interface are described in the CPU External Bus Specification. The preceding table highlights 82443BX specific uses
of these signals.
■ ■ ■ ■ Host Signals Not supported by the 82443BX
Signal
Function
A[35:32]#
Address
AERR#
Address Parity Error
AP[1:0]#
Address Parity
BINIT#
Bus Initialization
DEP[7:0]#
Data Bus ECC/Parity
IERR#
Internal Error
INIT#
Soft Reset
BERR#
Bus Error
RP#
Request Parity
RSP#
Response Parity Signal Parity protection on RS[2:0]#
2) DRAM Interface
■ ■ ■ ■ DRAM Interface Signals
Name
Type
RASA[5:0]#
O
/CSA[5:0]#
CMOS
RASB[5:0]#
/CSB[5:0]#
CKE[3:2]
O
/CSA[7:6]#
CMOS
CKE[5:4]
/CSB[7:6]#
CASA[7:0]#
O
/DQMA[7:0]
CMOS
CASB[1,5]#
O
/DQMB[1,5]
CMOS
Hit Modified: Indicates that a caching agent holds a modified version of the requested line and that this agent assumes
responsibility for providing the line. Also driven in conjunction with HIT# to extend the snoop window.
Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and ADS#, until the negation of HLOCK# must
be atomic, i.e. no PCI or AGP snoopable access to DRAM is allowed when HLOCK# is asserted by the CPU.
Request Command: Asserted during both clocks of request phase. In the first clock, the signals define the transaction
type to a level of detail that is sufficient to begin a snoop request. In the second clock, the signals carry additional infor-
mation to define the complete transaction type. The transactions supported by the 82443BX Host Bridge are defined in
the Host Interface section of this document.
Host Target Ready: Indicates that the target of the CPU transaction is able to enter the data transfer phase.
Response Signals: Indicates type of response according to the following the table:
RS[2:0] Response type
000
Idle state
001
Retry response
010
Deferred response
011
Reserved (not driven by 82443BX)
100
Hard Failure (not driven by 82443BX)
101
No data response
110
Implicit Writeback
111
Normal data response
Extended addressing (over 4 GB)
Parity protection on address bus
Parity protection on address bus
Checking for bus protocol violation and protocol recovery mechanism
Enhanced data bus integrity
Direct internal error observation via IERR# pin
Implemented by PIIX4E, BIST supported by external logic.
Unrecoverable error without a bus protocol violation
Parity protection on ADS# and PREQ[4:0]#
Row Address Strobe (EDO): These signals are used to latch the row address on the MAxx lines into the DRAMs. Each
signal is used to select one DRAM row.
These signals drive the DRAM array directly without any external buffers.
Chip Select (SDRAM): For the memory row configured with SDRAM these pins perform the function of selecting the
particular SDRAM components during the active state.
Note that there are 2 copies of RAS# per physical memory row to improve the loading.
Clock Enable: In mobile mode, SDRAM Clock Enable is used to signal a self-refresh or power-down command to an
SDRAM array when entering system suspend. CKE is also used to dynamically power down inactive SDRAM rows.
This CKE function is not supported with Registered DIMMs.
Chip Select (SDRAM): These pins perform the function of selecting the particular SDRAM components during the
active state.
Note that there are 2 copies of CS# per physical memory row to reduce the loading.
Column Address Strobe A-side (EDO): The CASA[7:0]# signals are used to latch the column address on the MA[13:0]
lines into the DRAMs of the A half of the memory array. These are active low signals that drive the DRAM array directly
without external buffering.
Input/Output Data Mask A-side (SDRAM): These pins control A half of the memory array and act as synchronized out-
put enables during read cycles and as a byte enables during write cycles.
Column Address Strobe B-side (EDO) / Input/Output Data Mask B-side (SDRAM): The same function as a correspond-
ing signals for A side. These signals are used to reduce the loading in an ECC configuration
Description
Not Supported By 82443BX
Description
UP-5900VS CIRCUIT DESCRIPTION
5 – 13
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