Advertisement
Name
Type
PAR
I/O
PCI
PLOCK#
I/O
PCI
TRDY#
I/O
PCI
SERR#
I/O
PCI
STOP#
I/O
PCI
Note:
1. All PCI interface signals conform to the PCI Rev 2.1 specification.
4) Primary PCI Sideband Interface
■ ■ ■ ■ Primary PCI Sideband Interface Signals
Name
Type
PHOLD#
I
PCI
PHLDA#
O
PCI
WSC#
O
CMOS
PREQ[4:0]#
I
PCI
PGNT[4:0]#
O
PCI
5) AGP Interface Signals
There are 17 new signals added to the normal PCI group of signals that together constitute the AGP interface.
The sections below describe their operation and use, and are organized in five groups:
• AGP Addressing Signals
• AGP Flow Control Signals
• AGP Status Signals
• AGP Clocking Signals- Strobes
• PCI Signals
Parity: PAR is driven by the 82443BX when it acts as a PCI initiator during address and data phases for a write cycle,
and during the address phase for a read cycle. PAR is driven by the 82443BX when it acts as a PCI target during each
data phase of a PCI memory read cycle. Even parity is generated across AD[31:0] and C/BE[3:0]#.
Lock: PLOCK# indicates an exclusive bus operation and may require multiple transactions to complete. When
PLOCK# is asserted, non-exclusive transactions may proceed. The 82443BX supports lock for CPU initiated cycles
only. PCI initiated locked cycles are not supported.
Target Ready: TRDY# is an input when the 82443BX acts as a PCI initiator and an output when the 82443BX acts as a
PCI target. The assertion of TRDY# indicates the target agent's ability to complete the current data phase of the trans-
action.
System Error: The 82443BX asserts this signal to indicate an error condition. The SERR# assertion by the 82443BX is
enabled globally via SERRE bit of the PCICMD register.
SERR# is asserted under the following conditions:
In an ECC configuration, the 82443BX asserts SERR#, for single bit (correctable) ECC errors or multiple bit (non-cor-
rectable) ECC errors if SERR# signaling is enabled via the ERRCMD control register. Any ECC errors received during
initialization should be ignored.
• The 82443BX asserts SERR# for one clock when it detects a target abort during 82443BX initiated PCI cycle.
• The 82443BX can also assert SERR# when a PCI parity error occurs during the address or data phase.
• The 82443BX can assert SERR# when it detects a PCI address or data parity error on AGP.
• The 82443BX can assert SERR# upon detection of access to an invalid entry in the Graphics Aperture Translation
Table.
• The 82443BX can assert SERR# upon detecting an invalid AGP master access outside of AGP aperture and outside
of main DRAM range (i.e. in the 640k - 1M range or above TOM).
• The 82443BX can assert SERR# upon detecting an invalid AGP master access outside of AGP aperture.
• The 82443BX asserts SERR# for one clock when it detects a target abort during 82443BX initiated AGP cycle.
Stop: STOP# is an input when the 82443BX acts as a PCI initiator and an output when the 82443BX acts as a PCI tar-
get. STOP# is used for disconnect, retry, and abort sequences on the PCI Bus.
PCI Hold: This signal comes from the PIIX4E. It is the PIIX4E request for PCI bus ownership.
The 82443BX will flush and disable the CPU-to-PCI write buffers before granting the PIIX4E the PCI bus via PHLDA#.
This prevents bus deadlock between PCI and ISA.
PCI Hold Acknowledge: This signal is driven by the 82443BX to grant PCI bus ownership to the PIIX4E after CPU-PCI
post buffers have been flushed and disabled.
Write Snoop Complete. This signal is asserted active to indicate that all that the snoop activity on the CPU bus on the
behalf of the last PCI-DRAM write transaction is complete and that is safe to send the APIC interrupt message.
PCI Bus Request: PREQ[4:0]# are the PCI bus request signals used as inputs by the internal PCI arbiter.
PCI Grant: PGNT[4:0]# are the PCI bus grant output signals generated by the internal PCI arbiter.
Description
Description
UP-5900VS CIRCUIT DESCRIPTION
5 – 15
Advertisement
Chapters
