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Sharp UP-5900 Service Manual page 37

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7. PCI BUS
7-1. DEVICE NUMBER DECODE
Bus
Device
Func
IDSEL
Number
0000h
0000h
AD11
0001h
0000h
AD12
0000h
0001h
0
0007h
AD18
0002h
0003h
000Ah
0000h
AD21
0012h
XXXXh
AD29
1
0000h
0000h
AD16
7-2. BUS ARBITRATION
Master Device No.
Request allow signal
Device 0
REQ0#, GNT0#
Device 1
REQ1#, GNT1#
Device 2
REQ2#, GNT2#
Device 3
REQ3#, GNT3#
9. CPU
Intel's embedded Celeron (RB80526RX566128SL4PC) is used.
The clock frequency of CPU is automatically multiplied in the Chip.
System Bus, Core Frequency
Core Frequency (MHz)
566
The core voltage of CPU is automatically set by connecting the VID terminal to the power IC.
Voltage Identification Definition
VID3
VID2
0
1
Device
Remark
440BX
Host to PCI Bridge
PCI to PCI Bridge
PCI to ISA Bridge
IDE Interface
PIIX4e
USB Interface
Power Management
RTL8139C
LAN Controller
PCI SLOT
Expansion SLOT
Lynx3DM4+ VGA (AGP connection)
Device
(Not Used)
(Not Used)
(Not Used)
PCI Slot
BCLK Frequency (MHz)
66
VID1
VID0
1
UP-5900VS CIRCUIT DESCRIPTION
7-3. INTERRUPT REQUEST
PIRQ D
PIRQ A
PIRQ D is connected to the above PCI device and PCIIRQ0 of PCI
SLOT, and connected to IRQ2 by BIOS.
PIRQ A is connected to PCIIRQ1 of PCI SLOT, and connected to IRQ5
by BIOS.
Interrupt requests which can be used with PCI slot are limited to INTA#
(PCI) and INTB# (PCI). INTC# (PCI) and INTD# (PCI) must not be
used.
PCI Interrupt SelectionPIO
PIO PCIIRQ
PIO PCIIRQ0#
PIO PCIIRQ1#
PIO PCIIRQ2#
PIO PCIIRQ3#
8. SM BUS
Address
10100000b
10100010b
00110000b
LM84CIM
11010010b
Frequency Multiplier
8.5
VccCore
1
1.70
5 – 7
Lynx3DM4+
RTL8139CL PCI SLOT
VGA
LAN
Selection
IRQ12
IRQ5
Disable
Disable
Device
DIMM 0
UP-5900 standard memory supports SPD.
DIMM 1
DIMM can be set with SPD.
CPU Temperature SENSOR
ICS9248
Clock Generator
Celeron566
Step C
PIIX4e
USB
PCI Interrupt
INTA#
INTB#
INTC#
INTD#
Remark

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