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■ ■ ■ ■ POWER MANAGEMENT SIGNALS
Name
Type
BATLOW#/
I
GPI9
CPU_STP#/
O
GPO17
EXTSMI#
I/OD
LID/
I
GPI10
PCIREQ[A:D]#
I
PCI_STP#/
O
GPO18
PWRBTN#
I
RI#
I
GPI12
RSMRST#
I
SMBALERT#/
I
GPI11
SMBCLK
I/O
SMBDATA
I/O
SUSA#
O
SUSB#/
O
GPO15
SUSC#/
O
GPO16
SUS_STAT1#/
O
GPO20
SUS_STAT2#/
O
GPO21
THRM#/
I
GPI8
ZZ/
O
GPO19
BATTERY LOW. Indicates that battery power is low. PIIX4E can be programmed to prevent a resume operation
when the BATLOW# signal is asserted.
If the Battery Low function is not needed, this pin can be used as a general- purpose input.
CPU CLOCK STOP. Active low control signal to the clock generator used to disable the CPU clock outputs. If this
function is not needed, then this signal can be used as a general-purpose output.
For values During Reset, After Reset, and During POS, see the Suspend/Resume and Resume Control Signaling
section.
EXTERNAL SYSTEM MANAGEMENT INTERRUPT. EXTSMI# is a falling edge triggered input to PIIX4E indicating
that an external device is requesting the system to enter SMM mode. When enabled, a falling edge on EXTSMI#
results in the assertion of the SMI# signal to the CPU. EXTSMI# is an asynchronous input to PIIX4E. However,
when the setup and hold times are met, it is only required to be asserted for one PCICLK. Once negated EXTSMI#
must remain negated for at least four PCICLKs to allow the edge detect logic to reset. EXTSMI# is asserted by
PIIX4E in response to SMI# being activated within the Serial IRQ function. An external pull-up should be placed on
this signal.
LID INPUT. This signal can be used to monitor the opening and closing of the display lid of a notebook computer. It
can be used to detect both low to high transition or a high to low transition and these transitions will generate an
SMI# if enabled. This input contains logic to perform a 16-ms debounce of the input signal. If the LID function is not
needed, this pin can be used as a generalpurpose input.
PCI REQUEST. Power Management input signals used to monitor PCI Master Requests for use of the PCI bus.
They are connected to the corresponding REQ[0:3]# signals on the Host Bridge.
PCI CLOCK STOP. Active low control signal to the clock generator used to disable the PCI clock outputs. The
PIIX4E free running PCICLK input must remain on. If this function is not needed, this pin can be used as a general-
purpose output.
For values During Reset, After Reset, and During POS, see the Suspend/Resume and Resume Control Signaling
section.
POWER BUTTON. Input used by power management logic to monitor external system events, most typically a sys-
tem on/off button or switch. This input contains logic to perform a 16-ms debounce of the input signal.
RING INDICATE. Input used by power management logic to monitor external system events, most typically used for
wake up from a modem. If this function is not needed, then this signal can be individually used as a general-purpose
input.
RESUME RESET. This signal resets the internal Suspend Well power plane logic and portions of the RTC well logic.
SM BUS ALERT. Input used by System Management Bus logic to generate an interrupt (IRQ or SMI) or power man-
agement resume event when enabled. If this function is not needed, this pin can be used as a general-purpose
input.
SM BUS CLOCK. System Management Bus Clock used to synchronize transfer of data on SMBus.
During Reset: High-Z
After Reset: High-Z
SM BUS DATA. Serial data line used to transfer data on SMBus.
During Reset: High-Z
After Reset: High-Z
SUSPEND PLANE A CONTROL. Control signal asserted during power management suspend states. SUSA# is pri-
marily used to control the primary power plane. This signal is asserted during POS, STR, and STD suspend states.
During Reset: Low
After Reset: High
SUSPEND PLANE B CONTROL. Control signal asserted during power management suspend states. SUSB# is pri-
marily used to control the secondary power plane. This signal is asserted during STR and STD suspend states. If
the power plane control is not needed, this pin can be used as a general-purpose output.
During Reset: Low
After Reset: High
SUSPEND PLANE C CONTROL. Control signal asserted during power management suspend states, primarily used
to control the tertiary power plane.
It is asserted only during STD suspend state. If the power plane control is not needed, this pin can be used as a gen-
eral-purpose output.
During Reset: Low
After Reset: High
SUSPEND STATUS 1. This signal is typically connected to the Host-to-PCI bridge and is used to provide informa-
tion on host clock status. SUS_STAST1# is asserted when the system may stop the host clock, such as Stop Clock
or during POS, STR, and STD suspend states. If this function is not needed, this pin can be used as a general-pur-
pose output.
During Reset: Low
After Reset: High
SUSPEND STATUS 2. This signal will typically connect to other system peripherals and is used to provide informa-
tion on system suspend state. It is asserted during POS, STR, and STD suspend states. If this function is not
needed, this pin can be used as a general-purpose output.
During Reset: Low
After Reset: High
THERMAL DETECT. Active low signal generated by external hardware to start the Hardware Clock Throttling mode.
If enabled, the external hardware can force the system to enter into Hardware Clock Throttle mode by asserting
THRM#. This causes PIIX4E to cycle STPCLK# at a preset programmable rate. If this function is not needed, this
pin can be used as a general-purpose input.
LOW-POWER MODE FOR L2 CACHE SRAM. This signal is used to power down a cachefs data SRAMs when the
clock logic places the CPU into the Stop Clock.
If this function is not needed, this pin can be used as a general-purpose output.
During Reset: Low
After Reset: Low
UP-5900VS CIRCUIT DESCRIPTION
Description
During POS: High-Z
During POS: High-Z
During POS: Low
During POS: High/GPO
During POS: High/GPO
During POS: Low/GPO
During POS: Low/GPO
During POS: Low
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