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Signal
Type
SLOTOCC#
O
(S.E.P.P. only)
SLP#
I
SMI#
I
STPCLK#
I
TCK
I
TDI
I
TDO
O
TESTHI (S.E.P.P. only)
I
THERMDN
O
THERMDP
I
THERMTRIP#
O
TMS
I
TRDY#
I
TRST#
I
VCC1.5
I
(PGA packages only)
VCC2.5
I
(PGA packages only)
VCCCMOS
O
(PGA packages only)
VCOREDET
O
(PGA packages only)
VID[4:0]
O
VID[3:0]
(PGA packages only)
VREF[7:0]
I
(PGA packages only)
SLOTOCC# is defined to allow a system design to detect the presence of a terminator card or processor in a SC242
connector. This pin is not a signal; rather, it is a short to VSS. Combined with the VID combination of VID[4:0]= 11111 ,
a system can determine if a SC242 connector is occupied, and whether a processor core is present. The states and
values for determining the type of cartridge in the SC242 connector is shown below.
SC242 Occupation Truth Table
Signal
SLOTOCC#
VID[4:0]
SLOTOCC#
VID[4:0]
SLOTOCC#
VID[4:0]
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to enter the Sleep state. During Sleep
state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still
operating.
Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertions of the
SLP#, STPCLK#, and RESET# signals while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and
returns to Stop-Grant state, restarting its internal clock signals to the bus and APIC processor core units.
The SMI# (System Management Interrupt) signal is asserted asynchronously by system logic. On accepting a System
Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low power Stop-Grant state. The pro-
cessor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core
units except the bus and APIC units. The processor continues to snoop bus transactions and may latch interrupts while
in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units, resumes execu-
tion, and services any pending interrupt. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
The TCK (Test Clock) signal provides the clock input for the Intel Celeron processor Test Access Port.
The TDI (Test Data In) signal transfers serial test data into the processor. TDI provides the serial input needed for
JTAG specification support.
The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO provides the serial output needed
for JTAG specification support.
Thermal Diode p-n junction. Used to calculate core temperature.
Thermal Diode p-n junction. Used to calculate core temperature.
The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well
above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution
when the junction temperature exceeds approximately 135°C. This is signaled to the system by the THERMTRIP#
(Thermal Trip) pin. Once activated, the signal remains latched, and the processor stopped, until RESET# goes active.
There is no hysteresis built into the thermal sensor itself; as long as the die temperature drops below the trip level, a
RESET# pulse will reset the processor and execution will continue. If the temperature has not dropped below the trip
level, the processor will reassert THERMTRIP# and remain stopped. The system designer should not act upon THER-
MTRIP# until after the RESET# input is deasserted. Until this time, the THERMTRIP# is indeterminate.
The TMS (Test Mode Select) signal is a JTAG specification support signal used by debug tools.
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready to receive a write or implicit write-
back data transfer. TRDY# must connect the appropriate pins of all system bus agents.
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. Intel Celeron processors require this signal to
be driven low during power on Reset. A 680 ohm resistor is the suggested value for a pull down resistor on TRST#.
The VCCCMOS pin provides the CMOS voltage for use by the platform. The 2.5 V must be provided to the VCC2.5
input and 1.5 V must be provided to the VCC1.5 input.
The processor re-routes the 1.5 V input to the VCCCMOS output via the package. The supply for VCC1.5 must be the
same one used to supply VTT.
The V pin provides the CMOS voltage for use by the platform. The 2.5 V CCCMOS must be provided to the VCC2.5
input and 1.5 V must be provided to the VCC1.5 input.
The processor re-routes the 2.5 V input to the VCCCMOS output via the package.
The VCCCMOS pin provides the CMOS voltage for use by the platform. The 2.5 V must be provided to the VCC2.5
input and 1.5 V must be provided to the VCC1.5 input.
The VCOREDET signal will float for 2.0 V core processors and will be grounded for Celeron FC-PGA processor with a
1.5V core voltage.
The VID (Voltage ID) pins can be used to support automatic selection of power supply voltages. These pins are not sig-
nals, but are either an open circuit or a short(S.E.P.P.) circuit to VSS on the processor. The combination of opens and
shorts defines the voltage required by the processor. The VID pins are needed to cleanly support voltage specification
variations on Intel Celeron processors.
These input signals are used by the AGTL+ inputs as a reference voltage. AGTL+inputs are differential receivers and
will use this voltage to determine whether the signal is a logic high or logic low.
For the FC-PGA package, VREF is typically 2/3 of VTT
Description
Value
0
Anything other than '1111'
0
1111
1
Any value
UP-5900VS CIRCUIT DESCRIPTION
5 – 11
Status
Processor with core in SC242
connector.
Terminator cartridge in SC242
connector (i.e., no core present).
SC242 connector not occupied.
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