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17. POS SYSTEM CONTROLLER 2
This is connected to ISA bus by using Sharp's LZ9AM22, and used to
control POS devices.
Special System Register 1: 07F1h
SSR1
b7
b6
b5
Read
A9
A8
A7
Write
A9
A8
A7
bit7: Offset address (A9) default = 0 / UP-5900 = 0
bit6: Offset address (A8) default = 1 / UP-5900 = 1
bit5: Offset address (A7) default = 0 / UP-5900 = 1
bit4: Offset address (A6) default = 0 / UP-5900 = 0
Registers except for SSR0 (07F0h) and SSR1 (07F1h) inside
PSC2 can be set to Relocatable in the unit of 40h by the above off-
set address setup. Therefore the address of a relocatable register
is expressed as (PSC2+***h) =@@@h.
bit3: not used
bit2: not used
bit1: Shut Down Enable
SDEN = 0 : Enable (Default)
SDEN = 1 : Disable
bit0: not used
17-1. PSC2 FEATURE OUTLINE
Sharpfs LZ9A10000 is used as the PSC2, controlling the devices
connected to the ISA bus.
BIOS ROM control
MASK ROM control
ROM and RAM disk control
The PSC2 internally expands dedicated interrupts to allow ISA inter-
rupts
to be assigned.
Incorporated DOS convertible UART2 channel
Incorporated UART2 channel for VFD I/F
Incorporated UART1 channel for touch panel
Incorporated 2 channels of MCR I/F
Incorporated 4 channels of drawer I/F
Incorporated 2 channels of CKDC I/F
Incorporated mode key I/F and clerk key I/F
Supported input ports of system SW
Incorporated 2 channels of 8-bit timer counter
Decoded output of super I/O upper address
Reset control
b4
b3
b2
b1
A6
0
0
SDEN
A6
0
0
SDEN
UP-5900VS CIRCUIT DESCRIPTION
17-2. MEMORY CONTROL (NOT USED)
17-3. I/O CONTROL
(1) Special System Register
The special system register has a input port reading setup data defin-
b0
ing the system configuration of hardware and software, offset register
0
setting a base address to relocatably place each internal register of the
0
PSC2 on the I/O space, COM decode control register, and shut-down
register.
This special system register uses fixed I/O address ranging from 07F0H
to 07F1H. This address is in the area used by the FDC, however this
address is non-selected address of super I/O. So sys-tems using the
PSC2 are limited to a system in which address 07F0H to 07F1H is not
selected as an address decoded by the FDC, or a system which uses
the super I/O chip.
(2) Interrupt Expansion and Assign Control
The interrupt control lines on the ISA bus used in the PSC2 are 6 lines:
IRQ3, IRQ4, IRQ9, IRQ10, IRQ11, and IRQ15.
Each interrupt control line is outputted by taking OR between signals on
the ISA bus and the interrupt signal in the PSC2. UART2 can be
assigned to IRQ2, and UART1 can be assigned to IRQ4. PC-X dedi-
cated interrupt (IRQX) can be assigned to IRQ9. UART1, 2, and 5 can
be assigned to IRQ10 and 11. UART1/2 and IRQX can be as-signed to
IRQ15.
IRQX is a signal generated by taking OR among interrupt control from
the POS dedicated device.
Assignment to each IRQ is controlled according to the setting of inter-
rupt assign register 0 and 1 (IAR0 and 1).
The PSC2 internal interrupt expansion consists of a maskable inter-rupt
source register (ISR), which is the source of interface OR-com-posed
from each interrupt input, interrupt mask register (IMR) control-ling the
mask control, status read level register (SRL) reading the status of input
which is not masked, status read register (SRR) read-ing edges, and
status clear register (SCR) generating edges for the next interrupt.
INT EVENT
SRL
LEVEL
IBM-PCfs 8259 is programmed based on rising edges and incor-
porates edge generators on the rear step of each interrupt handling of
level input. Edges are generated based on the output of OR-composi-
tion when performing dummy writing to the SCR.
The steps generating an edge for general interrupts are as follows:
1) Read the ISR.
2) Check the factor of interrupt.
3) Perform the handling of interrupt for each factor.
4) Write clear the corresponding SCR bit to generate the following
edge.
Read in interrupt disable state and clear the corresponding bit to "1"
to write.
5) Return from the interrupt handling.
5 – 42
MASKABLE
IMR
FF
SCR
SRR
ISR
EDGE
OR GATE
IRQ9/15
DATA BUS
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