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Signal/Pin
Pin Number
Name
BUSY
66
CFG0
92
CLKIN
33
CTS2,1
93,83
D7-0
8-1
DACK3
42
DACK2,1
39,38
DCD2,1
94,84
DENSEL
97, 48 or 44
DIR
50
DR1,0
48, 47
DRATE0
95, 45 or 43
DRQ3-1
37-35
DSKCHG
58
DSR2,1
95,85
DSTRB
74
DTR2,1
96,86
ERR
71
HDSEL
52
I/O and
Module
Group #
Parallel Port
Input
Group 2
Configuration
Input
Group 4
Clock
Input
Group 1
UART1,
Input
UART2
Group 1
ISA-Bus
I/O
Group 5
ISA-Bus
Input
Group 1
UART1,
Input
UART2
Group 1
FDC
Output
Group 11
FDC
Output
Group 11
FDC
Output
Group 11
FDC
Output
Group 14
ISA-Bus
Output
Group 13
FDC
Input
Group 1
UART1,
Input
UART2
Group 1
Parallel Port
Output
Group 8
UART1,
Output
UART2
Group 12
Parallel Port
Input
Group 3
FDC
Output
Group 11
Busy – This pin is set high by the printer when it cannot accept another character. It is
internally connected to a weak pull-down resistor.
This signal is multiplexed with WAIT.
This pin selects between Full-IR and Two-UART mode as the default configuration
upon power up. It is pulled down by internal 30 KΩ resistors. External 10 KW pull-up
resistors to VDD should be employed.
This signal is multiplexed with SOUT1.
Clock In – A TTL or CMOS compatible 48 MHz clock.
UART1 and UART2 Clear to Send – When low, these signals indicate that the modem
or other data transfer device is ready to exchange data.
CTS2 is multiplexed with A11, and available only in Two-UART mode.
ISA-Bus Data – Bidirectional data lines to the microprocessor. D0 is the LSB and D7 is
the MSB. These signals have 24 mA (sink) buffered outputs.
DMA Acknowledge 1,2 and 3 – These active low input signals
acknowledge a request for DMA services and enable the IOWR and IORD input signals
during a DMA transfer. These DMA signals can be mapped to the following logical
devices: FDC, UART or Parallel Port.
UART1 and UART2 Data Carrier Detected – When low, this signal indicates that the
modem or other data transfer device has detected the data carrier.
DCD2 is multiplexed with P12 and available only in Two-UART mode.
Density Select – Indicates that a high FDC density data rate (500 Kbps or 1 Mbps) or a
low density data rate (250 or 300 Kbps) is selected.
DENSEL polarity is controlled by bit 5 of the SuperI/O FDC Configuration register as
described in Section 2.5.1.
This signal is multiplexed with: IRTX, , DR1, or R12.
Direction – This output signal determines the direction of the Floppy Disk Drive (FDD)
head movement (active = step in, inactive = step out) during a seek operation. During
reads or writes, DIR is inactive.
Drive Select 0 and 1 – These active low output signals are the decoded drive select
output signals. DR0 and DR1 are controlled by Digital Output Register (DOR) bits 0
and 1. They are encoded with information to control four FDDs when bit 7 of the
SuperI/O FDC Configuration register is 1, as described in Section 2.5.1.
DR0 can optionally become a logical OR of DR0 and MTR0 when MTR0/DRATE0 is
used as DRATE0.
DR1 is multiplexed with DENSEL and is available only in Two-UART mode. Optionally,
it can become a logical OR of DR1 and MTR1 when MTR1/P12 is used as P12.
Data Rate 0 – This output signal reflects the value of bit 0 of the Configuration Control
Register (CCR) or the Data Rate Select Register (DSR), whichever was written to last.
Output from the pin is totem-pole buffered (6 mA sink, 6 mA source).
This signal is multiplexed with IRRX1/P12, MTR0 or DSR2
DMA Request 1, 2 and 3 – These active high output signals inform the DMA controller
that a data transfer is needed. These DMA signals can be mapped to the following log-
ical devices: Floppy Disk Controller (FDC), UART or parallel port.
Disk Change – This input signal indicates whether or not the drive door has been
opened. The state of this pin is available from the Digital Input Register (DIR). This pin
can also be configured as the RGATE data separator diagnostic input signal via the
MODE command.
Data Set Ready – When low, this signal indicates that the data transfer device, e.g.,
modem, is ready to establish a communications link.
DSR2 is multiplexed with DRATE0 and available only in Two-UART mode.
Data Strobe – This signal is used in EPP mode as a data strobe. It is active low.
DSTRB is multiplexed with AFD.
Data Terminal Ready – When low, this output signal indicates to the modem or other
data transfer device that the UART1 or UART2 is ready to establish a communications
link.
A Master Reset (MR) deactivates this signal high, and loopback operation holds this
signal inactive.
DTR1 is multiplexed with BADDR0 and with BOUT1.
DTR2 is multiplexed with IRSL2/ID2/BOUT2 and is available only in Two-UART mode.
(BOUT2 is multiplexed implicitly and controlled by UART2.)
Error – This input signal is set active low by the printer when it has detected an error.
This pin is internally connected to an internal weak pull-up.
Head Select – This output signal determines which side of the FDD is accessed. Active
low selects side 1, inactive selects side 0.
UP-5900VS CIRCUIT DESCRIPTION
5 – 39
Function
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