Kontron COMe-cEL6 User Manual page 80

Sub-screen Next Level Sub-screens / Description
System Agent
CPU Crash Log
(SA) (Device 10)>
Configuration>
CRID Support>
(continued)
Above 4 GB
MMIO BIOS
Assignment>
Sub-screen Next level Sub-Screens / Description
PCH-IO PCI Express
Configuration>
Configuration>
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[Enabled, Disabled]
SA CRID and TCSS CRID control for Intel SIPP
[Enabled, Disabled]
Enables automatically when aperture size is set to 2048 MB.
[Enabled, Disabled]
DMI Link ASPM Control of Active State power management of the DMI
Control>
[Disable, L0s, L1, L0sL1, Auto]
[Enabled, Disabled]
Peer Memory
Write Enable>
Compliance [Enabled, Disabled]
Test Mode>
PCH PCI Express PCH PCI express clock gating (power management) for
Clock Gating> each root port.
[Platform-POR, Enabled, Disabled]
PCIe Function Disabled prevents PCIe root port function swap. If any
Swap> function other than 0
[Enabled, Disabled]
PCIe EQ PCIe EQ Override>
Settings>
PCIE Express PCIe Express Root
Root Port Port [#]>
[1 to 5]>
Connection Type>
ASPM>
L1 Sub-states>
ACS>
COMe-cEL6 - User Guide, Rev.1.2
th is enabled, 0 th will become visible.
Choose PCIe EQ setting. Only use
when you have a thorough
understanding of the equalization
process.
[Enabled, Disabled]
Control the PCIe Express Root Port
[Enabled, Disabled]
Built-in: A built-in device is
connected to this root port. Slot
implemented bit will be clear.
Slot: This root port connects to a
user accessible slot. Slot
implemented boot will be set.
[Built-in, Slot]
Sets ASPM level:
Force LO: Forces all links to L0 state
Auto: BIOS auto configure
Disable: Disables ASPM
[Disable, L0s, L1, LOsL1, Auto]
PCIe L1 sub-state settings:
[Disabled, l1.1, l1.1 &L1.2]
Access Control Service
[Enabled, Disabled]
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