ABB Relion 650 Series Applications Manual page 87

1MRK 505 287-UUS B
different overcurrent protections is normally enabled by co-ordination between the operate time
of the different protections. To enable optimal co-ordination all overcurrent protections, to be co-
ordinated against each other, should have the same time characteristic. Therefore a wide range of
standardized inverse time characteristics are available: IEC and ANSI. The time characteristic for
step 1 and 4 can be chosen as definite time delay or inverse time characteristic. Step 2 and 3 are
always definite time delayed and are used in system where IDMT is not needed.
Table 11:
Curve name
ANSI Extremely Inverse
ANSI Very Inverse
ANSI Normal Inverse
ANSI Moderately Inverse
ANSI/IEEE Definite time
ANSI Long Time Extremely Inverse
ANSI Long Time Very Inverse
ANSI Long Time Inverse
IEC Normal Inverse
IEC Very Inverse
IEC Inverse
IEC Extremely Inverse
IEC Short Time Inverse
IEC Long Time Inverse
IEC Definite Time
ASEA RI
RXIDG (logarithmic)
Power transformers can have a large inrush current, when being energized. This inrush current can
have residual current components. The phenomenon is due to saturation of the transformer
magnetic core during parts of the cycle. There is a risk that inrush current will give a residual
current that reaches level above the pickup current of the residual overcurrent protection. The
inrush current has a large second harmonic content. This can be used to avoid unwanted
operation of the protection. Therefore, EF4PTOC (51N_67N) has a possibility of second harmonic
restrain
of the fundamental current.
7.2.3 Setting guidelines
Busbar protection REB650
Application manual
Time characteristics
2ndHarmStab if the level of this harmonic current reaches a value above a set percentage
When inverse time overcurrent characteristic is selected, the operate time of the
stage will be the sum of the inverse time delay and the set definite time delay.
Thus, if only the inverse time delay is required, it is important to set the definite
time delay for that stage to zero.
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Section 7
Current protection
M15282-3 v6.1.1
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