ABB Relion 650 Series Applications Manual page 189

1MRK 505 287-UUS B
11.3.2 Application
A set of standard logic blocks, like AND, OR etc, and timers are available for adapting the IED
configuration to the specific application needs.
There are no settings for AND gates, OR gates, inverters or XOR gates.
For normal On/Off delay and pulse timers the time delays and pulse lengths are set from the local
HMI or via the PST tool.
Both timers in the same logic block (the one delayed on pick-up and the one delayed on drop-out)
always have a common setting value.
For controllable gates, settable timers and SR flip-flops with memory, the setting parameters are
accessible via the local HMI or via the PST tool.
11.3.3.1 Configuration
Logic is configured using the ACT configuration tool in PCM600.
Execution of functions as defined by the configurable logic blocks runs according to a fixed
sequence with different cycle times.
For each cycle time, the function block is given an serial execution number. This is shown when
using the ACT configuration tool with the designation of the function block and the cycle time, see
example below.
IEC09000695 V2 EN-US
Figure 96: Example designation, serial execution number and cycle time for logic function
The execution of different function blocks within the same cycle is determined by the order of
their serial execution numbers. Always remember this when connecting two or more logical
function blocks in series.
Busbar protection REB650
Application manual
IEC09000695_2_en.vsd
© Copyright 2013 ABB. All rights reserved
Section 11
Logic
GUID-F5D6F065-441B-4296-AC56-F4DC1F5487E3 v3
GUID-E6BD982D-9E47-4CC2-9666-6E5CABA414C0 v2
GUID-D93E383C-1655-46A3-A540-657141F77CF0 v3
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