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6.27 Host-Port Interface (UHPI)
6.27.1 HPI Device-Specific Information
The device includes a user-configurable 16-bit Host-port interface (HPI16). See the TMS320C6745/C6747
DSP Peripherals Overview Reference Guide. (SPRUFK9) for more details.
6.27.2 HPI Peripheral Register Description(s)
BYTE ADDRESS
0x01E1 0000
0x01E1 0004
0x01E1 0008
0x01E1 000C
0x01E1 0010
0x01E1 0014
0x01E1 0018
0x01E1 001C
0x01E1 0020
0x01E1 0024
01E1 0028
01E1 002C
01E1 0030
01E1 0034
01E1 0038
01E1 000C - 01E1 07FF
(1) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that
HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the
perspective of the Host. The CPU can access HPIAW and HPIAR independently.
Copyright © 2008–2014, Texas Instruments Incorporated
Table 6-98. HPI Control Registers
ACRONYM
PID
Peripheral Identification Register
PWREMU_MGMT
HPI power and emulation management register
-
Reserved
GPIO_EN
General Purpose IO Enable Register
GPIO_DIR1
General Purpose IO Direction Register 1
GPIO_DAT1
General Purpose IO Data Register 1
GPIO_DIR2
General Purpose IO Direction Register 2
GPIO_DAT2
General Purpose IO Data Register 2
GPIO_DIR3
General Purpose IO Direction Register 3
GPIO_DAT3
General Purpose IO Data Register 3
-
Reserved
-
Reserved
HPIC
HPI control register
HPIA
HPI address register
(1)
(HPIAW)
(Write)
HPIA
HPI address register
(1)
(HPIAR)
(Read)
-
Reserved
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Product Folder Links:
TMS320C6745 TMS320C6747
SPRS377F – SEPTEMBER 2008 – REVISED JUNE 2014
REGISTER DESCRIPTION
Peripheral Information and Electrical Specifications
TMS320C6745, TMS320C6747
COMMENTS
The CPU has read/write
access to the
PWREMU_MGMT register.
The Host and the CPU both
have read/write access to the
HPIC register.
The Host has read/write
access to the HPIA registers.
The CPU has only read
access to the HPIA registers.
193
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