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(3) Multiplex Bus Timing
Table 5.4 and Figure 5.3 show the bus timing in memory expansion and microprocessor modes (with
wait, accessing external area, using multiplex bus).
Table 5.4 Memory expansion and microprocessor modes (with wait, accessing external area, using multiplex bus)
Symbol
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
th(RD-AD)
Address output hold time (RD standard)
th(WR-AD)
Address output hold time (WR standard)
td(BCLK-CS)
Chip-select output delay time
th(BCLK-CS)
Chip-select output hold time (BCLK standard)
th(RD-CS)
Chip-select output hold time (RD standard)
th(WR-CS)
Chip-select output hold time (WR standard)
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (BCLK standard)
th(BCLK-DB)
Data output hold time (BCLK standard)
td(DB-WR)
Data output delay time (WR standard)
th(WR-DB)
Data output hold time (WR standard)
td(BCLK-ALE)
ALE output delay time (BCLK standard)
th(BCLK-ALE)
ALE output hold time (BCLK standard)
td(AD-ALE)
ALE output delay time (Address standard)
th(ALE-AD)
ALE output hold time (Address standard)
td(AD-RD)
After address RD signal output delay time
td(AD-WR)
After address WR signal output delay time
tdz(RD-AD)
Address output floating start time
*1 Calculated by the following formula accord-
ing to the frequency of BCLK.
10
th(RD-AD)=
f(BCLK)x2
10
th(WR-AD)=
f(BCLK)x2
10
th(RD-CS)=
f(BCLK)x2
10
th(WR-CS)=
f(BCLK)x2
9
10
th(DB-WR)=
f(BCLK)x2
10
th(WR-DB)=
f(BCLK)x2
10
th(AD-ALE)=
f(BCLK)x2
Item
9
+0 [ns]
9
+0 [ns]
9
+0 [ns]
9
+0 [ns]
x3
-50 [ns]
9
+0 [ns]
9
-40 [ns]
( 65 / 84 )
Actual MCU
[ns]
Min.
4
(*1)
(*1)
4
(*1)
(*1)
0
0
4
(*1)
(*1)
-4
(*1)
30
0
0
*2 Calculated by the following formula accord-
ing to the frequency of BCLK.
9
10
th(WR-AD)=
f(BCLK)x2
9
10
th(WR-CS)=
f(BCLK)x2
10
9
th(WR-DB)=
f(BCLK)x2
This product
[ns]
Max.
Min.
Max.
50
See left
See left
See left
(*2)
50
See left
See left
(*2)
(*2)
40
See left
See left
40
See left
See left
50
See left
See left
(*2)
(*2)
40
See left
See left
See left
See left
-4
-3
8
17
-6 [ns]
-6 [ns]
-12 [ns]
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