Timing Requirements - Renesas Emulation Pod M3062NT3-RPD-E User Manual

(4) Timing Requirements

Table 5.5 and Figure 5.4 show the timing requirements.
Table 5.5 Timing requirements
Symbol
tsu(DB-RD) Data input setup time
tsu(RDY-BCLK) RDY* input setup time
tsu(HOLD-BCLK) HOLD* input setup time
th(RD-DB) Data input hold time
th(BCLK-RDY) RDY* input hold time
th(BCLK-HOLD) HOLD* input hold time
td(BCLK-HLDA) HLDA* output delay time
Common to "with wait" and "no-wait" (actual MCU)
Common to "with wait" and "no-wait" (this product)
Note 1. P00 to P52 will be high-impedance status regardless of the input level of pin BYTE and ports
P40 to P43 function selection bit (PM06) of the processor mode register 0.
Note 2. Compared with the actual MCU, this product enters high-impedance state after a 0.5 cycle
delay.
Figure 5.4 Timing requirements
Item
Conditions:
• VCC = 3.3 V
• Input timing voltage: VIL = 0.66 V, VIH = 2.64 V
• Output timing voltage: VOL = 1.65 V, VOH = 1.65 V
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Actual MCU This product
[ns] [ns]
Min. Max. Min.
65
50
50 65
115
100
0
See left
0
See left
0
See left
40
See left
Max.