Texas Instruments SimpleLink CC3220MOD Series Manual page 65

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P50_GPIO_00
P55_GPIO_01
P57_GPIO_02
At a minimum, pull thes pins out
P58_GPIO_03
to test points to aid in debug:
P59_GPIO_04
Pin 48: CC_ W L_RS232_TX
P60_GPIO_05
Pin 49: CC_WL_RS232_RX
P61_GPIO_06
Pin 50: CC_WL_UART_TX
P62_GPIO_07
Pin 52: CC_NP W_UART_TX
P63_GPIO_08
P64_GPIO_09
P01_GPIO_10
P02_GPIO_11
P03_GPIO_12
P04_GPIO_13
P05_GPIO_14
P06_GPIO_15
P07_GPIO_16
P08_GPIO_17
P15_GPIO_22
P18_GPIO_28
P53_GPIO_30
For the board files and BOM, see the LAUNCHXL-CC3220MODSF.
Copyright © 2021 Texas Instruments Incorporated
U7
44
GPIO_0 VBAT1
46
GPIO_01
47
GPIO_02 VBAT2
48
GPIO_03
49
GPIO_04
50
GPIO_05
51
GPIO_06 VBAT_RESET
52
GPIO_07
53
GPIO_08 RESET
54
GPIO_09
3
GPIO_10
4
GPIO_11 JTAG_TDI
9
GPIO_12 JTAG_TDO
10
GPIO_13 JTAG_TCK
5
GPIO_14 JTAG_TMS
6
GPIO_15
7
GPIO_16
8
GPIO_17
11
GPIO_22 RF_BG
19
GPIO_28
42
GPIO_30
ANT_SEL1
ANT_SEL2
1
GND
2
GND
16
GND SOP0
27
GND SOP1
28
GND SOP2
30
GND
32
GND
38
GND FLASH_SPI_CLK
43
GND FLASH_SPI_CS_IN
55
GND FLASH_SPI_MOSI
56
GND FLASH_SPI_MISO
57
GND
58
GND NC
59
GND NC
60
GND NC
61
GND NC
62
GND NC
63
GND NC
CC3220MODSF12MOBR
GND
Figure 10-1. CC3220MODx Typical Application Schematic
Product Folder Links:
VCC
C3
0.1µF
GND
C4
0.1µF
37
40
GND
SEE TABLE 4-1 FOR
36
VBAT_RESET and nRESET
35 CONNECTION OPTIONS
JTAG_TDI
12
JTAG /
18 JTAG_TDO
21 JTAG_TCK DEBUG
JTAG_TMS
22
31
25
P29_GPIO_26
26
P30_GPIO_27
SOP[2:0] USED FOR
FACTORY RESTORE
34
24
23
SFL_CLK
15
SFL_nCS EXTERNAL
14
17 SFL_MOSI PROGRA MMING
13 SFL_MISO
20
29
33
39
41
45
CC3220MOD CC3220MODA
CC3220MOD, CC3220MODA
SWRS206E – MARCH 2017 – REVISED MAY 2021
Optional:
Consider adding extra decoupling
capacitors if the battery cannot source
the peak cu rrents.
VCC
C6 C7
100µF 100µF
GND GND
Matching circuit shown below is for
the antenna. The module is matched
internally to 50 . Final solution Ω
may require antenna matching
optimization with a pi-network
L1
3.3nH
C2
1pF
VCC
R1
GND
270
1 2
3 4
5 6
J1
Copyright © 2017, Texas Instruments Incorporated
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E1
GND GND
65