Texas Instruments SimpleLink CC3220MOD Series Manual page 45

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PARAMETER
Input impedance
Number of channels
F Sampling rate of each pin
sample
F_input_max Maximum input signal frequency
SINAD Signal-to-noise and distortion
I_active Active supply current
Power-down supply current for
I_PD
core supply
Absolute offset error
Gain error
V ADC reference voltage
ref
8.14.5.7 Camera Parallel Port
The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in a
FIFO, and generates DMA requests. The camera parallel port supports 8 bits.
Figure 8-16 shows the timing diagram for the camera parallel port.
pCLK
pVS, pHS
pDATA
Table 8-14 lists the timing parameters for the camera parallel port.
ITEM
pCLK
T2 T
clk
T3 t
LP
T4 t
HT
T6 t
IS
T7 t
IH
8.14.5.8 UART
The CC3220MODx and CC3220MODAx modules include two UARTs with the following features:
• Programmable baud-rate generator allowing speeds up to 3 Mbps
• Separate 16-bit × 8-bit TX and RX FIFOs to reduce CPU interrupt service loading
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Table 8-13. ADC Electrical Specifications (continued)
DESCRIPTION
ADC Pin 57
ADC Pin 58
ADC Pin 59
ADC Pin 60
Input frequency DC to 300 Hz
and 1.4 V
Average for analog-to-digital
during conversion without
reference current
Total for analog-to-digital when
not active (this must be the SoC
level test)
FCLK = 10 MHz
T3 T2
Figure 8-16. Camera Parallel Port Timing Diagram
Table 8-14. Camera Parallel Port Timing Parameters
NAME
Clock frequency
Clock period
Clock low period
Clock high period
RX data setup time
RX data hold time
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TEST CONDITIONS /
ASSUMPTIONS
sine wave input
pp
T4
T6
DESCRIPTION
CC3220MOD CC3220MODA
CC3220MOD, CC3220MODA
SWRS206E – MARCH 2017 – REVISED MAY 2021
MIN TYP MAX
2.15
0.7
2.12
1.17
4
62.5
31
55 60
1.5
1
±2
±2%
1.467
T7
MIN MAX
2
1/pCLK
T /2
clk
T /2
clk
2
2
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UNIT
kΩ
KSPS
kHz
dB
mA
µA
mV
V
UNIT
MHz
ns
ns
ns
ns
ns
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