Texas Instruments SimpleLink CC3220MOD Series Manual page 44

CC3220MOD, CC3220MODA
SWRS206E – MARCH 2017 – REVISED MAY 2021
Table 8-12 lists the JTAG timing parameters.
ITEM NAME
T1 f
TCK
T2 t
TCK
T3 t
CL
T4 t
CH
T7 t
TMS_SU
T8 t
TMS_HO
T9 t
TDI_SU
T10 t
TDI_HO
T11 t
TDO_HO
8.14.5.6 ADC
Table 8-13 lists the ADC electrical specifications. See
ADC and for application-specific examples.
ADC CLOCK
= 10 MHz
Sampling SAR Conversion
4 cycles 16 cycles
EXT CHANNEL 0
Figure 8-15 shows the ADC clock timing diagram.
PARAMETER
Nbits Number of bits
INL Integral nonlinearity
DNL Differential nonlinearity
Input range
Driving source
impedance
FCLK Clock rate
Input capacitance
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Table 8-12. JTAG Timing Parameters
DESCRIPTION
Clock frequency
Clock period
Clock low period
Clock high period
TMS setup time
TMS hold time
TDI setup time
TDI hold time
TDO hold time
Repeats Every 16 µs
Internal Ch
2 µs 2 µs 2 µs
Sampling SAR Conversion
4 cycles 16 cycles
INTERNAL CHANNEL
Figure 8-15. ADC Clock Timing Diagram
Table 8-13. ADC Electrical Specifications
DESCRIPTION
Worst-case deviation from
histogram method over full scale
(not including first and last three
LSB levels)
Worst-case deviation of any step
from ideal
Successive approximation input
clock rate
Product Folder Links:
CC32xx ADC Appnote
2 µs 2 µs 2 µs
Sampling SAR Conversion
4 cycles 16 cycles
EXT CHANNEL 1
TEST CONDITIONS /
ASSUMPTIONS
CC3220MOD CC3220MODA
MIN MAX
1 / f
TCK
t
TCK
t
TCK
1
16
1
16
for further information on using the
2 µs 2 µs 2 µs
Sampling SAR Conversion
4 cycles 16 cycles
INTERNAL CHANNEL
MIN TYP
12
–2.5
–1
0
10
12
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UNIT
15 MHz
ns
/ 2 ns
/ 2 ns
ns
ns
ns
ns
15 ns
2 µs
MAX UNIT
Bits
2.5 LSB
4 LSB
1.4 V
100 Ω
MHz
pF