Texas Instruments SimpleLink CC3220MOD Series Manual page 43

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2
Table 8-11 lists the I C timing parameters.
ITEM NAME
T2 t
LP
T3 t
SRT
T4 t
DH
T5 t
SFT
T6 t
HT
T7 t
DS
T8 t
SCSR
T9 t
SCS
(1) This value depends on the value programmed in the clock period register of I
value programmed in this register.
2
(2) Because I C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of external pullup. Rise time depends on
the value of the external signal capacitance and external pullup register.
(3) All timing is with 6-mA drive and 20-pF load.
8.14.5.5 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and
boundary scan architecture for digital integrated circuits and provides a standardized serial interface to control
the associated test logic. For detailed information on the operation of the JTAG port and TAP controller, see the
IEEE Standard 1149.1,Test Access Port and Boundary-Scan Architecture.
Figure 8-14 shows the JTAG timing diagram.
TCK
TMS
TDI
TDO
Copyright © 2021 Texas Instruments Incorporated
Table 8-11. I
DESCRIPTION
Clock low period
SCL/SDA rise time
Data hold time
SCL/SDA fall time
Clock high time
Data setup time
Start condition setup time
Stop condition setup time
T2
T7 T8
TMS Input Valid
T9 T10
TDI Input Valid
T11
TDO Output Valid
Figure 8-14. JTAG Timing Diagram
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2 (3)
C Timing Parameters
2
C. Maximum output frequency is the result of the minimal
T3
T7
TMS Input Valid
T9
TDI Input Valid
T1
TDO Output Valid
CC3220MOD CC3220MODA
CC3220MOD, CC3220MODA
SWRS206E – MARCH 2017 – REVISED MAY 2021
MIN MAX
(1)
See
(2)
See
NA
3
(1)
See
tLP/2
36
24
T4
T8
T10
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UNIT
System clock
ns
ns
System clock
System clock
System clock
System clock
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